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eess.SP updates on arXiv.org

ECG-biometrics-bench: A Unified Framework for Reproducible Benchmarking of ECG Biometrics Physiology-Aware Masked Cross-Modal Reconstruction for Biosignal Representation Learning Towards Improving Speaker Distance Estimation through Generative Impulse Response Augmentation Federated Learning with Hypergradient-based Online Update of Aggregation Weights Soft Graph Diffusion Transformer for MIMO Detection SPLICE: Latent Diffusion over JEPA Embeddings for Conformal Time-Series Inpainting Sequential Inference for Gaussian Processes: A Signal Processing Perspective Statistical Channel Fingerprint Construction for Massive MIMO: A Unified Tensor Learning Framework Recent Advances in mm-Wave and Sub-THz/THz Oscillators for FutureG Technologies Cross-Subject Generalization for EEG Decoding: A Survey of Deep Learning Methods Super-resolution Multi-signal Direction-of-Arrival Estimation by Hankel-structured Sensing and Decomposition Hankel and Toeplitz Rank-1 Decomposition of Arbitrary Matrices with Applications to Signal Direction-of-Arrival Estimation Adaptive Transform Coding for Semantic Compression EdgeSpike: Spiking Neural Networks for Low-Power Autonomous Sensing in Edge IoT Architectures Sparse Graph Learning from Sparse Data via Fiedler Number Maximization A Deep Learning Model for Battery State Prediction towards Intelligent Energy Management Transfer Learning for Tonal Noise Prediction in VRF Units Using Thermodynamic and Vibration Signals EVT-Based Generative AI for Tail-Aware Channel Estimation Monitoring exposure-length variations in submarine power cables using distributed fiber-optic sensing BandRouteNet: An Adaptive Band Routing Neural Network for EEG Artifact Removal Phase-Separated Complex Hilbert PCA on Markerless 3D Pose Estimation Data: A Global Phase Network and Its Extension to a Continuous Field on the Body Surface Selective Correlation Based Knowledge Distillation for Ground Reaction Force Estimation Deep Learning-Enabled Dissolved Oxygen Sensing in Biofouling Environments for Ocean Monitoring Speech Enhancement Based on Drifting Models Robust and Clinically Reliable EEG Biomarkers: A Cross Population Framework for Generalizable Parkinson's Disease Detection An AI-Based Supervisory Measurement Integrity Validation Layer for Cyber-Resilient AC/DC Protection in Inverter-Based Microgrids Explainable AI in Speaker Recognition -- Making Latent Representations Understandable Time-Localized Parametric Decomposition of Respiratory Airflow for Sub-Breath Analysis NAKUL-Med: Spectral-Graph State Space Models with Dynamics Kernels for Medical Signals An Algorithm for On-Sensor Agnostic Detection of Changes in Human Activity for Ultra-Low-Power Applications
Benchmarking and Validation of Sub-mW 30GHz VG-LNAs in 22...
Domenico Zito, Michele Spasaro · 2024-09-11 · via eess.SP updates on arXiv.org

Next-generation (5G/6G) wireless systems demand low-power mm-wave phased-array ICs. Variable-gain LNAs (VGLNAs) are key building blocks enabling hardware complexity reduction, performance enhancement and functionality extension. This paper reports a performance benchmarking of two low-power 30GHz VG-LNAs for phased-array ICs, which provide a 7.5dB gain control for 18dB Taylor taper in a 30GHz 8x8 antenna array, for a comprehensive validation of the new class of VGLNAs and its design methodology. In particular, this paper reports a second and implementation (VG-LNA2) with a reduced number (four) of gain-control back-gate voltages and super-low-Vt MOSFETs, with respect to the previous first implementation (VG-LNA1) with six gain-control back-gate voltages and regular- Vt MOSFETs, both in the same 22nm FDSOI CMOS technology. The results show that VG-LNA2 exhibits performance comparable to those of VG-LNA1, with a slightly lower power consumption. Overall, the performance benchmarking shows that the design methodology adopted for the new class of VG-LNAs leads to record low-power consumption and small form factor solutions reaching the targeted performances, regardless of the arrangements of the back-gate voltages for gain control and transistor sets, resulting in a comprehensive validation of the innovative design features and effective design methodology.