Complex digital systems such as high performance computers (HPCs) make extensive use of high-speed electrical interconnects, in routing signals among processing elements, or between processing elements and memory. Despite increases in serializer/deserializer (SerDes) and memory interface speeds, there is demand for higher bandwidth busses in constrained physical spaces which still mitigate simultaneous switching noise (SSN). The concept of zero sum signaling utilizes coding across a data bus to allow the use of single-ended buffers while still mitigating SSN, thereby reducing the number of physical channels (e.g. circuit board traces) by nearly a factor of two when compared with traditional differential signaling. Through simulation and analysis of practical (non-ideal) data bus and power delivery network architectures, we demonstrate the feasibility of zero sum signaling and compare performance with that of traditional (single-ended and differential) methods.