The detector readout architecture introduced in this paper is intended for small to medium size physics experiments that have moderate bandwidth needs, and applications that require an ultimately low background radioactivity for the parts close to the detector. The first idea to simplify the readout system and minimize material budget is to use a common fanout structure to transport from the off-detector back-end electronics all the traffic required for the synchronization, configuration and readout of the front-end electronics. The second idea is to use between each front-end card and the back-end electronics a point-to-point link that runs at the relatively low speed that suffices for the target application. This broadens the possible choices for the physical media of the communication links, e.g. glass fiber, plastic optical fiber, or copper. This paper presents a communication protocol adequate for the proposed asymmetric network and shows the design of a back-end unit capable of controlling 32 front-end units at up to 12.8 Gbps of aggregate bandwidth using an inexpensive commercial FPGA module where the large number of regular I/O pins interface to the front-end links, while the few available multi-gigabit per second capable transceivers are affected to the communication with the upper stage of the DAQ system.