The thesis work presents assertion based functional verification of RTL representation of a digital design. The MBIST controller is designed based on a memory testing March algorithm. This March algorithm is a little modified March C algorithm which is modified by adding a paused element to test memory data retention faults. In assertion based functional verification, creation of verification plan, for MBIST controller RTL model and the implementation & simulation of the verification plan using System-Verilog and Synopsys-VCS are done. In ABV, verification plan includes the MBIST controller design and functional specification, functional coverage goals, code coverage goals, and assertions. Assertions are used to check the errors in RTL model of MBIST controller and to provide the functionality coverage. Functional coverage metrics are used to track the level or quality of verification. Most of the functional metrics score approximately reached the planned goal of 100 % which is planned in the verification plan. The designed MBIST controller is verified against the intended features. ABV approach helped to make the verification and design process efficient and less time-consuming by finding the bugs, exercising the corner cases in the design, and using the directed test cases in a small design. ABV helped to write directed and efficient test cases (25) which are approx 32 % less than the use of maximum possible random test cases (88) for designed MBIST controller with 100% assertion coverage and approximately equal total functional coverage, i.e., 97 % approx. In this way, ABV helped to fasten the design and verification process with better quality and assurance of correct functionality of MBIST controller after the integration in MBIST architecture.