Abstract:Signal Temporal Logic (STL), has recently seen extensive development, owing to its rich expressivenes for autonomous planning and control. Nevertheless, existing verification and control synthesis methods are limited with respect to the complexity and degree of nesting of the formulae. In this work, we propose a novel approach to STL based on an operator acting on reachability value functions. This constitutes a new theoretical framework for handling complex multi-nested formulae while at the same time providing tools for on-line control synthesis. In contrast to focusing on the design of STL-based reachability (or control barrier) functions, we develop operator-based nesting rules directly. Our method's expressiveness is demonstrated both theoretically, where necessary and sufficient conditions for STL formula satisfaction are extracted, as well as in simulations with complex fragments.
From: Panagiotis Rousseas Dr. [view email]
[v1]
Wed, 27 May 2026 07:47:45 UTC (761 KB)
[v2]
Mon, 29 Jun 2026 11:44:18 UTC (1 KB) (withdrawn)
[v3]
Fri, 7 Aug 2026 10:09:23 UTC (751 KB)
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