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cs.NE updates on arXiv.org

MPCS: Neuroplastic Continual Learning via Multi-Component Plasticity and Topology-Aware EWC Combining Trained Models in Reinforcement Learning Training Non-Differentiable Networks via Optimal Transport ShiftLIF: Efficient Multi-Level Spiking Neurons with Power-of-Two Quantization Probe-Geometry Alignment: Erasing the Cross-Sequence Memorization Signature Below Chance Benchmarking local Hebbian learning rules for memory storage and prototype extraction Robust volatility updates for Hierarchical Gaussian Filtering Spiking Sequence Machines and Transformers Affinity Is Not Enough: Recovering the Free Energy Principle in Mixture-of-Experts Scalable Learning in Structured Recurrent Spiking Neural Networks without Backpropagation Geometric and dynamical analysis of attractor boundaries and storage limits in kernel Hopfield networks Attractor FCM Physical Foundation Models: Fixed hardware implementations of large-scale neural networks When Does Structure Matter in Continual Learning? Dimensionality Controls When Modularity Shapes Representational Geometry Learning to Forget: Continual Learning with Adaptive Weight Decay Causal Learning with Neural Assemblies NORACL: Neurogenesis for Oracle-free Resource-Adaptive Continual Learning Text-Utilization for Encoder-dominated Speech Recognition Models EdgeSpike: Spiking Neural Networks for Low-Power Autonomous Sensing in Edge IoT Architectures EvoTSC: Evolving Feature Learning Models for Time Series Classification via Genetic Programming Analysis and Explainability of LLMs Via Evolutionary Methods Deployment-Aligned Low-Precision Neural Architecture Search for Spaceborne Edge AI SeaEvo: Advancing Algorithm Discovery with Strategy Space Evolution Primitive Recursion without Composition: Dynamical Characterizations, from Neural Networks to Polynomial ODEs MAEO: Multiobjective Animorphic Ensemble Optimization for Scalable Large-scale Engineering Applications Necessary and sufficient conditions for universality of Kolmogorov-Arnold networks Learn&Drop: Fast Learning of CNNs based on Layer Dropping Architecture-Induced Recoverability Bias in Differentiable Symbolic Regression Collocation-based Robust Physics Informed Neural Networks for time-dependent simulations of pollution propagation under thermal inversion conditions on Spitsbergen Structure-Guided Diffusion Model for EEG-Based Visual Cognition Reconstruction
The Brain on Low Power Architectures - Efficient Simulati...
Roberto Ammendola, Andrea Biagioni, Fabrizio Capuani, Paolo Cret · 2018-04-10 · via cs.NE updates on arXiv.org

Efficient brain simulation is a scientific grand challenge, a parallel/distributed coding challenge and a source of requirements and suggestions for future computing architectures. Indeed, the human brain includes about 10^15 synapses and 10^11 neurons activated at a mean rate of several Hz. Full brain simulation poses Exascale challenges even if simulated at the highest abstraction level. The WaveScalES experiment in the Human Brain Project (HBP) has the goal of matching experimental measures and simulations of slow waves during deep-sleep and anesthesia and the transition to other brain states. The focus is the development of dedicated large-scale parallel/distributed simulation technologies. The ExaNeSt project designs an ARM-based, low-power HPC architecture scalable to million of cores, developing a dedicated scalable interconnect system, and SWA/AW simulations are included among the driving benchmarks. At the joint between both projects is the INFN proprietary Distributed and Plastic Spiking Neural Networks (DPSNN) simulation engine. DPSNN can be configured to stress either the networking or the computation features available on the execution platforms. The simulation stresses the networking component when the neural net - composed by a relatively low number of neurons, each one projecting thousands of synapses - is distributed over a large number of hardware cores. When growing the number of neurons per core, the computation starts to be the dominating component for short range connections. This paper reports about preliminary performance results obtained on an ARM-based HPC prototype developed in the framework of the ExaNeSt project. Furthermore, a comparison is given of instantaneous power, total energy consumption, execution time and energetic cost per synaptic event of SWA/AW DPSNN simulations when executed on either ARM- or Intel-based server platforms.