Geospatial Processing, such as queries based on point-to-polyline shortest distance and point-in-polygon test, are fundamental to many scientific and engineering applications, including post-processing large-scale environmental and climate model outputs and analyzing traffic and travel patterns from massive GPS collections in transportation engineering and urban studies. Commodity parallel hardware, such as multi-core CPUs, many-core GPUs and Intel MIC accelerators, provide enormous computing power which can potentially achieve significant speedups on existing geospatial processing and open the opportunities for new applications. However, the realizable potential for geospatial processing on these new hardware devices is largely unknown due to the complexity in porting serial algorithms to diverse parallel hardware platforms. In this study, we aim at experimenting our data-parallel designs and implementations of point-to-polyline shortest distance computation (P2P) and point-in-polygon topological test (PIP) on different commodity hardware using real large-scale geospatial data, comparing their performance and discussing important factors that may significantly affect the performance. Our experiments have shown that, while GPUs can be several times faster than multi-core CPUs without utilizing the increasingly available SIMD computing power on Vector Processing Units (VPUs) that come with multi-core CPUs and MICs, multi-core CPUs and MICs can be several times faster than GPUs when VPUs are utilized. By adopting a Domain Specific Language (DSL) approach to exploiting the VPU computing power in geospatial processing, we are free from programming SIMD intrinsic functions directly which makes the new approach more effective, portable and scalable. Our designs, implementations and experiments can serve as case studies for parallel geospatial computing on modern commodity parallel hardware.