Minimizing wire-lengths is one of the most important objectives in circuit design. The process involves initially placing the logical units (cells) of a circuit onto a physical layout, and subsequently routing the wires to connect the cells. Hypergraph partitioning (HGP) has been long used as a placement strategy in this process. However, it has been replaced by other methods due to the limitation that common HGP objective funtions only optimize wire-lengths implicitly. In this work, we present a novel HGP formulation that maps a hypergraph $H$, representing a logical circuit, onto a routing layout represented by a weighted graph $G$. The objective is to minimize the total length of all wires induced by the hyperedges of $H$ on $G$. To capture wire-lengths, we compute minimal Steiner trees - a metric commonly used in routing algorithms. For this formulation, we present the first direct $k$-way multilevel mapping algorithm that incorporates techniques used by the highest-quality partitioning algorithms. We contribute a greedy mapping algorithm to compute an initial solution and three refinement algorithms to improve the initial: Two move-based local search heuristics (based on label propagation and the FM algorithm) and a refinement algorithm based on max-flow min-cut computations. Our experiments demonstrate that our new algorithm achieves an improvement in the Steiner tree metric by 7% (median) on VLSI instances when compared to the best performing partitioning algorithm that optimizes the mapping in a postprocessing step. Although computing Steiner trees is an NP-hard problem, we achieve this improvement with only a 2-3 times slowdown in partitioning time compared to optimizing the connectivity metric.