The miss rate of TLB is crucial to the performance of address translation for virtual memory. To reduce the TLB misses, improving translation coverage of TLB has been an primary approach. Many previous works focus on coalescing multiple contiguously mapped pages of the memory mapping into a modified entry, which function well if the assumed contiguity of memory mapping is given. Unfortunately, scenarios of applications are complicated and the produced contiguity diversify. To gain better performance of translation, in this paper, we first introduce a complex but prevalent type of contiguity, mixed contiguity. Then we propose a HW-SW hybrid coalesced TLB structure which works well on all observed types of contiguity including this type. In our evaluation, the proposed scheme, K-bit Aligned TLB, outperforms the state-of-the-art work by reducing at lease 27% TLB misses on average over it using 16 benchmarks.