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cs.DC updates on arXiv.org

DUAL-BLADE: Dual-Path NVMe-Direct KV-Cache Offloading for Edge LLM Inference Progressive Semantic Communication for Efficient Edge-Cloud Vision-Language Models Efficient, VRAM-Constrained xLM Inference on Clients Folding Tensor and Sequence Parallelism for Memory-Efficient Transformer Training & Inference DORA: A Scalable Asynchronous Reinforcement Learning System for Language Model Training AMMA: A Multi-Chiplet Memory-Centric Architecture for Low-Latency 1M Context Attention Serving RaMP: Runtime-Aware Megakernel Polymorphism for Mixture-of-Experts Spark Policy Toolkit: Semantic Contracts and Scalable Execution for Policy Learning in Spark Internet of Everything in the 6G Era: Paradigms, Enablers, Potentials and Future Directions PolyKV: A Shared Asymmetrically-Compressed KV Cache Pool for Multi-Agent LLM Inference A Survey on Split Learning for LLM Fine-Tuning: Models, Systems, and Privacy Optimizations ITAS: A Multi-Agent Architecture for LLM-Based Intelligent Tutoring Latency and Cost of Multi-Agent Intelligent Tutoring at Scale TACO: Efficient Communication Compression of Intermediate Tensors for Scalable Tensor-Parallel LLM Training FreeScale: Distributed Training for Sequence Recommendation Models with Minimal Scaling Cost CommFuse: Hiding Tail Latency via Communication Decomposition and Fusion for Distributed LLM Training A Taxonomy and Resolution Strategy for Client-Level Disagreements in Federated Learning Usable Agent Discovery for Decentralized AI Systems Cloud to Edge: Benchmarking LLM Inference On Hardware-Accelerated Single-Board Computers Data-Free Contribution Estimation in Federated Learning using Gradient von Neumann Entropy Shard the Gradient, Scale the Model: Serverless Federated Aggregation via Gradient Partitioning Promoting Simple Agents: Ensemble Methods for Event-Log Prediction GraphLeap: Decoupling Graph Construction and Convolution for Vision GNN Acceleration on FPGA AGNT2: Autonomous Agent Economies on Interaction-Optimized Layer 2 Infrastructure FedSIR: Spectral Client Identification and Relabeling for Federated Learning with Noisy Labels Stream-CQSA: Avoiding Out-of-Memory in Attention Computation via Flexible Workload Scheduling A Delta-Aware Orchestration Framework for Scalable Multi-Agent Edge Computing Federated Learning over Blockchain-Enabled Cloud Infrastructure Optimal Routing for Federated Learning over Dynamic Satellite Networks: Tractable or Not? Sherpa.ai Privacy-Preserving Multi-Party Entity Alignment without Intersection Disclosure for Noisy Identifiers
Segregated FLS Processing Cores for V/STOL Autonomous Lan...
Hossam O. Ahmed · 2023-06-06 · via cs.DC updates on arXiv.org

It is highly predicted that the roads and parking areas will be extremely congested with vehicles to the point that searching for a novel solution will not be an optional choice for conserving the sustainability rate of the overall humanity's development growth. Such issue could be overcome by developing modified generations of the Urban Air Mobility (UAM) vehicles that essentially depend on the Vertical and/or Short Take-Off and Landing (V/STOL) feature to increase the efficiency of landing capabilities on limited-space parking areas. The complexity of integrating an efficient and safe V/STOL feature in such UAM vehicles is notably difficult comparing with the conventional and normal techniques for landing and take-off. The efficient V/STOL feature should be carried out by a complete and collaborative Cyber-Physical System (CPS) processing architecture, such as the CPS-5C architecture. In this paper, we only proposed two CPS-5C physical layers of a V/STOL Autonomous Landing Guidance Assistant System (ALGAS2) processing unit to increase the reliability of the vertical landing mechanism. The proposed V/STOL-ALGAS2 system depends on Fuzzy Logic System (FLS) as the advanced control unit. Furthermore, the proposed ALGAS2 system depends on four symmetric and segregated processing ALGAS2 cores that processing the data in a fully parallel and independent manner to enhance many essential security and safety factors for the futuristic UAM vehicles. The proposed ALGAS2 digital circuits architecture has been designed using MATLAB and VHDL. Also, it has been further analyzed for the implementation and validation tests using the Intel Altera OpenVINO FPGA board. The proposed ALGAS processing unit attained a maximum computational processing performance of about 21.22 Giga Operations per Seconds (GOPS).