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Agentic Vulnerability Reasoning on Windows COM Binaries From Beats to Breaches:How Offensive AI Infers Sensitive User Information from Playlists Undetectable Backdoors in Model Parameters: Hiding Sparse Secrets in High Dimensions When Embedding-Based Defenses Fail: Rethinking Safety in LLM-Based Multi-Agent Systems Token-Efficient Change Detection in LLM APIs Selfie-Capture Dynamics as an Auxiliary Signal Against Deepfakes and Injection Attacks for Mobile Identity Verification Trident: Improving Malware Detection with LLMs and Behavioral Features When Alignment Isn't Enough: Response-Path Attacks on LLM Agents RefusalGuard: Geometry-Preserving Fine-Tuning for Safety in LLMs Checkerboard: A Simple, Effective, Efficient and Learning-free Clean Label Backdoor Attack with Low Poisoning Budget Block-wise Codeword Embedding for Reliable Multi-bit Text Watermarking Secret Stealing Attacks on Local LLM Fine-Tuning through Supply-Chain Model Code Backdoors Enhancing Linux Privilege Escalation Attack Capabilities of Local LLM Agents Defusing the Trigger: Plug-and-Play Defense for Backdoored LLMs via Tail-Risk Intrinsic Geometric Smoothing Evaluating Jailbreaking Vulnerabilities in LLMs Deployed as Assistants for Smart Grid Operations: A Benchmark Against NERC Standards Behavioral Canaries: Auditing Private Retrieved Context Usage in RL Fine-Tuning FlexServe: A Fast and Secure LLM Serving System for Mobile Devices with Flexible Resource Isolation Breaking MCP with Function Hijacking Attacks: Novel Threats for Function Calling and Agentic Models Text Steganography with Dynamic Codebook and Multimodal Large Language Model An AI Agent Execution Environment to Safeguard User Data TwoHamsters: Benchmarking Multi-Concept Compositional Unsafety in Text-to-Image Models Fundamental Limitations of Favorable Privacy-Utility Guarantees for DP-SGD Symbolic Guardrails for Domain-Specific Agents: Stronger Safety and Security Guarantees Without Sacrificing Utility Hardening x402: PII-Safe Agentic Payments via Pre-Execution Metadata Filtering QShield: Securing Neural Networks Against Adversarial Attacks using Quantum Circuits Hijacking Text Heritage: Hiding the Human Signature through Homoglyphic Substitution Like a Hammer, It Can Build, It Can Break: Large Language Model Uses, Perceptions, and Adoption in Cybersecurity Operations on Reddit Private Seeds, Public LLMs: Realistic and Privacy-Preserving Synthetic Data Generation One Word at a Time: Incremental Completion Decomposition Breaks LLM Safety Measuring and Exploiting Contextual Bias in LLM-Assisted Security Code Review
Global Microprocessor Correctness in the Presence of Tran...
Andrew T. Walter, Konstantinos Athanasiou, Panagiotis Manolios · 2025-06-21 · via cs.CR updates on arXiv.org

Correctness for microprocessors is generally understood to be conformance with the associated instruction set architecture (ISA). This is the basis for one of the most important abstractions in computer science, allowing hardware designers to develop highly-optimized processors that are functionally "equivalent" to an ideal processor that executes instructions atomically. This specification is almost always informal, e.g., commercial microprocessors generally do not come with conformance specifications. In this paper, we advocate for the use of formal specifications, using the theory of refinement. We introduce notions of correctness that can be used to deal with transient execution attacks, including Meltdown and Spectre. Such attacks have shown that ubiquitous microprocessor optimizations, appearing in numerous processors for decades, are inherently buggy. Unlike alternative approaches that use non-interference properties, our notion of correctness is global, meaning it is single specification that: formalizes conformance, includes functional correctness and is parameterized by an microarchitecture. We introduce action skipping refinement, a new type of refinement and we describe how our notions of refinement can be decomposed into properties that are more amenable to automated verification using the the concept of shared-resource commitment refinement maps. We do this in the context of formal, fully executable bit- and cycle-accurate models of an ISA and a microprocessor. Finally, we show how light-weight formal methods based on property-based testing can be used to identify transient execution bugs.