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Agentic Vulnerability Reasoning on Windows COM Binaries From Beats to Breaches:How Offensive AI Infers Sensitive User Information from Playlists Undetectable Backdoors in Model Parameters: Hiding Sparse Secrets in High Dimensions When Embedding-Based Defenses Fail: Rethinking Safety in LLM-Based Multi-Agent Systems Token-Efficient Change Detection in LLM APIs Selfie-Capture Dynamics as an Auxiliary Signal Against Deepfakes and Injection Attacks for Mobile Identity Verification Trident: Improving Malware Detection with LLMs and Behavioral Features When Alignment Isn't Enough: Response-Path Attacks on LLM Agents RefusalGuard: Geometry-Preserving Fine-Tuning for Safety in LLMs Checkerboard: A Simple, Effective, Efficient and Learning-free Clean Label Backdoor Attack with Low Poisoning Budget Block-wise Codeword Embedding for Reliable Multi-bit Text Watermarking Secret Stealing Attacks on Local LLM Fine-Tuning through Supply-Chain Model Code Backdoors Enhancing Linux Privilege Escalation Attack Capabilities of Local LLM Agents Defusing the Trigger: Plug-and-Play Defense for Backdoored LLMs via Tail-Risk Intrinsic Geometric Smoothing Evaluating Jailbreaking Vulnerabilities in LLMs Deployed as Assistants for Smart Grid Operations: A Benchmark Against NERC Standards Behavioral Canaries: Auditing Private Retrieved Context Usage in RL Fine-Tuning FlexServe: A Fast and Secure LLM Serving System for Mobile Devices with Flexible Resource Isolation Breaking MCP with Function Hijacking Attacks: Novel Threats for Function Calling and Agentic Models Text Steganography with Dynamic Codebook and Multimodal Large Language Model An AI Agent Execution Environment to Safeguard User Data TwoHamsters: Benchmarking Multi-Concept Compositional Unsafety in Text-to-Image Models Fundamental Limitations of Favorable Privacy-Utility Guarantees for DP-SGD Symbolic Guardrails for Domain-Specific Agents: Stronger Safety and Security Guarantees Without Sacrificing Utility Hardening x402: PII-Safe Agentic Payments via Pre-Execution Metadata Filtering QShield: Securing Neural Networks Against Adversarial Attacks using Quantum Circuits Hijacking Text Heritage: Hiding the Human Signature through Homoglyphic Substitution Like a Hammer, It Can Build, It Can Break: Large Language Model Uses, Perceptions, and Adoption in Cybersecurity Operations on Reddit Private Seeds, Public LLMs: Realistic and Privacy-Preserving Synthetic Data Generation One Word at a Time: Incremental Completion Decomposition Breaks LLM Safety Measuring and Exploiting Contextual Bias in LLM-Assisted Security Code Review
The Blockchain Based Auditor on Secret key Life Cycle in ...
Rourab Paul, Nimisha Ghosh, Amlan Chakrabarti, Prasant Mahapatra · 2020-07-13 · via cs.CR updates on arXiv.org

The growing sophistication of cyber attacks, vulnerabilities in high computing systems and increasing dependency on cryptography to protect our digital data make it more important to keep secret keys safe and secure. Few major issues on secret keys like incorrect use of keys, inappropriate storage of keys, inadequate protection of keys, insecure movement of keys, lack of audit logging, insider threats and non-destruction of keys can compromise the whole security system dangerously. In this article, we have proposed and implemented an isolated secret key memory which can log life cycle of secret keys cryptographically using blockchain (BC) technology. We have also implemented a special custom bus interconnect which receives custom crypto instruction from Processing Element (PE). During the execution of crypto instructions, the architecture assures that secret key will never come in the processor area and the movement of secret keys to various crypto core is recorded cryptographically after the proper authentication process controlled by proposed hardware based BC. To the best of our knowledge, this is the first work which uses blockchain based solution to address the issues of the life cycle of the secret keys in hardware platform. The additional cost of resource usage and timing complexity we spent to implement the proposed idea is very nominal. We have used Xilinx Vivado EDA tool and Artix 7 FPGA board.