• April 9, 2026

This week CNBC published a video by journalist-producer Katie Tarasov about advanced semiconductor packaging. I’ve had the opportunity to provide commentary for a number of Tarasov’s longer features, which give her more room to explore important topics in the chip industry while including multiple expert viewpoints. You can click the link below to see the video on YouTube, or read on for an AI-generated, human-edited overview and summary.

Link to edited segment.

Overview

Advanced packaging has emerged as a critical bottleneck in the global semiconductor industry, moving from an engineering afterthought to a primary driver of artificial intelligence chip performance. Historically concentrated in Asia, this process allows multiple chips and high bandwidth memory to be interconnected in 2.5-D and 3-D configurations, overcoming physical limitations of traditional silicon. TSMC currently dominates the market with its CoWoS technology, which is heavily reserved by NVIDIA to meet insatiable AI demand. To address supply constraints and geopolitical risks, leading-edge manufacturers TSMC and Intel are expanding domestic packaging capabilities in the United States, especially in Arizona.

Outline

The Shift to Advanced Semiconductor Packaging

• Katie Tarasov of CNBC notes that advanced packaging has become a major bottleneck in the race to power artificial intelligence.
• Paul Rousseau of TSMC explains that the process involves building silicon, obtaining high bandwidth memory from vendors, and employing an organic interposer for assembly.
• Tarasov observes that TSMC currently sends nearly every chip back to Taiwan for packaging, though the company is breaking ground on two new packaging plants in Arizona.
• Patrick Moorhead of Moor Insights & Strategy remarks that packaging used to be an afterthought — something handled by junior engineers — but is now considered as important as the silicon die itself.
• Jan Vardaman of TechSearch emphasizes that it is impossible to ship a modern silicon product without first putting it through the packaging step.

Technical Evolution from 2-D to 3-D Chip Packaging

• Rousseau compares the history of packaging to soda containers, where the primary function remains protecting and containing the product while the technology evolves.
• Moorhead describes how advanced packaging allows multiple chips manufactured with different technologies to be pulled into one large unit via interconnects.
• Tarasov explains the technical process of adding metallic bumps to the silicon surface and placing dies onto a resin-based substrate.
• Rousseau details 2.5-D packaging, such as TSMC’s own CoWoS (chip on wafer on substrate) approach, which uses an interposer as a communication channel to bring memory right beside the compute chip.
• Rousseau explains 3-D technology like SoIC, where chips are stacked on top of each other to lower power consumption and increase datacenter efficiency.

Market Demand for Advanced Chip Packaging and NVIDIA’s Dominance

• Tarasov reports that NVIDIA has reserved the majority of TSMC’s CoWoS capacity, forcing TSMC to outsource some work to third-party providers.
• Market researcher John VerWey warns that packaging can emerge as a bottleneck quickly if companies do not make proactive capital investments to account for fab output.
• Vardaman attributes current shortages to an unexpected surge in AI demand that exceeded existing capacity plans.
• Rousseau acknowledges that capacity has been tight and states that TSMC is responding by increasing CoWoS capacity at an 80% growth rate.
• Rousseau also asserts that despite high demand from major players, TSMC still strives to be a foundry for everyone in the industry.

Competitive Strategies and Geopolitics

• Tarasov highlights that Intel is a major alternative player, using EMIB technology in facilities across New Mexico and Arizona.
• Mark Gardner of Intel suggests that his company’s packaging capabilities provide a cost advantage and serve as an entry point for customers like Amazon and Cisco.
• Moorhead points out that national security concerns, including geopolitical tensions in Taiwan and Korea, are driving the push for U.S.-based manufacturing.
• Tarasov notes that Elon Musk has tapped Intel to package future custom chips for SpaceX, xAI, and Tesla.

Companies Mentioned

• TSMC
• NVIDIA
• Intel
• Micron
• Samsung
• SK Hynix
• MediaTek
• Amkor and SPIL
• ASE
• Amazon
• Cisco
• Google
• SpaceX
• Tesla
• xAI

Keyword Summary

semiconductor packaging, TSMC, advanced packaging, chipmaking, CoWoS, EMIB, HBM, high bandwidth memory, Intel, NVIDIA, chip foundry

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