A few weeks back, I was showing my PDP-8/e project at the Vintage Computer Festival in Zurich. While I was doing my project, I haven’t really checked if there were other projects like this. At least for the PDP-8 I knew there wasn’t, the only FPGA core I could find was a new implementation of the architecture that is binary compatible but doesn’t attempt to replicate the structure and instruction cycles of any specific PDP-8.

At this VCFe I found there were two other projects that also aim at recreating computers in FPGAs from original schematics. One is a DEC PDP-6, the other is an IBM System/360 Model 30. The IBM one is also interesting in that it appears to create a live image of the front panel state on its VGA output. At the VCFe however, it was connected to an original front panel, making it much more impressive.

From talking to the people involved in these projects I gathered that they have some challenges with the lack of a central clock that drives synchronous logic, a design method that is central to modern logic and the kind of hardware that can most efficiently be implemented in FPGAs. Apparently there are many places where logic delays were integral to both the PDP’s and IBM’s logic, and those are not simple to implement especially when the delay is not well documented in the schematics.

The PDP-8/e I am recreating also has logic running off of generated logic signals that are used as clock signals for flip-flops all over the place. However, all this is backed by a well defined timing phase and timing pulse generator backed by a 20 MHz oscillator. I found converting the schematics to synchronous logic rather straightforward as I have elaborated on here.