Such a system already exists

Posted May 28, 2026 14:13 UTC (Thu) by neggles (subscriber, #153254)
Parent article: Tier-aware memory-controller limits

Intel made a number of Xeon Max SKUs (primarily for the Aurora supercomputer) with on-package HBM as well as off-package DDR5, and Fujitsu have an upcoming HPC CPU (Monaka-X) which will have HBM, DDR5, and accelerator memory pools, for example

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