Abstract:FPGA-level emulation is a key step in pre-silicon chip design validation. However, emulating large-scale multi-core systems increasingly exceed the hardware resource capacity of a single FPGA, limiting the feasibility of full-system emulation. To address this challenge, we introduce EMiX, a scalable multi-FPGA framework that enables distributed emulation of multi-core RISC-V architectures beyond single-FPGA resource limits. EMiX systematically partitions a monolithic multi-core design into multiple components and deploys them across multiple interconnected FPGAs, effectively exploiting inter-FPGA interconnects to balance scalability and performance without requiring fundamental RTL redesign. We prototype EMiX with a 64-core architecture across eight interconnected Alveo U55c FPGAs (scalable on core and FPGA counts), successfully demonstrating full-system execution including Linux boot. EMiX will be released as an open-source platform.
| Comments: | RISC-V Summit EU 2026 |
| Subjects: | Hardware Architecture (cs.AR) |
| Cite as: | arXiv:2604.27012 [cs.AR] |
| (or arXiv:2604.27012v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2604.27012 arXiv-issued DOI via DataCite |
From: Behzad Salami [view email]
[v1]
Wed, 29 Apr 2026 10:32:10 UTC (704 KB)
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