Introduction

In this article, which our team will regularly update, we will maintain a growing list of information pertaining to upcoming hardware releases based on leaks and official announcements as we spot them. There will obviously be a ton of rumors on unreleased hardware, and it is our goal to—based on our years of industry experience—exclude the crazy ones. In addition to these upcoming hardware release news, we will regularly adjust the structure of this article to better organize information. Each time an important change is made to this article, it will re-appear on our front page with a "new" banner, and the additions will be documented in the forum comments thread. This article will not leak information we signed an NDA for.

Feel free to share your opinions and tips in the forum comments thread and subscribe to the same thread for updates.

Last Update (May 19th):

• Removed launched products: AMD Ryzen 9 9950X3D2 Dual Edition, NVIDIA RTX 5070 Mobile 12 GB
• Added AMD Ryzen 7 7700X3D
• Updated AMD Ryzen 9 Pro 9965X3D
• Updated AMD Zen 6
• Updated AMD Zen 7
• Updated Intel Nova Lake
• Updated Intel Razer Lake
• Updated Intel Diamond Rapids
• Updated NVIDIA GeForce RTX 5050 9 GB
• Updated NVIDIA GeForce RTX 3060 Samsung 8 nm
• Updated NVIDIA GeForce RTX 60-series (Rubin)
• Added AMD Radeon RX 9050
• Updated NVIDIA Vera Rubin
• Updated NVIDIA DLSS 5
• Updated Microsoft Xbox "Project Helix"
• Updated Sony PlayStation 6
• Updated Nintendo Switch 2 Updates
• Updated Valve Steam Machine
• Updated Valve Steam Deck 2
• Updated TSMC 1.4 nanometer
• Updated Intel 14A
• Updated Elon Musk "Terafab"
• Updated HBM4 Memory
• Updated HBM4E Memory
• Updated DDR6 System Memory
• Updated LPDDR6 Memory
• Updated NVIDIA SOCAMM Memory
• Updated ASRock HUDIMM Memory
• Updated PCI Express 8.0
• Added Valve Steam Frame
• Added Intel Serpent Lake
• Added Intel HB3DM Memory
• Added TSMC 1.3 nanometer
• Added TSMC 1.2 nanometer
• Added AMD Ryzen AI Max+ PRO "Gorgon Halo"

Processors

AMD Ryzen 7 7700X3D [added]

• Release Date: Unknown
• Zen 4 based, 8 cores / 16 threads, 96 MB L3 cache (32 MB on-die + 64 MB 3D V-Cache) #
• 4.00 GHz base / 4.50 GHz boost (downclocked 7800X3D) #
• Socket AM5 #
• Positioned between Ryzen 7 5800X3D and Ryzen 7 9800X3D #

AMD Ryzen 9 Pro 9965X3D [updated]

• 16 cores #
• 170 W TDP #
• Officially announced as part of expanded Ryzen PRO 9000 lineup with 6 new SKUs #
• 32 threads, up to 5.5 GHz boost, 128 MB L3 cache (3D V-Cache) #
• Also includes Ryzen 7 PRO 9755X3D (8 cores, 96 MB L3, 120 W) #
• Launching H2 2026 #

AMD Ryzen 7 9750X / Ryzen 5 9650X

• Release Date: Unknown
• Ryzen 7 9750X: 8 cores / 16 threads, 4.20 / 5.60 GHz, 120 W TDP #
• Ryzen 5 9650X: 6 cores / 12 threads, 4.30 / 5.50 GHz, 120 W TDP #
• Zen 5, Socket AM5, 32 MB L3 cache #
• Higher clocks and TDP vs existing Ryzen 7 9700X / Ryzen 5 9600X #

AMD Ryzen AI Max+ PRO "Gorgon Halo" [added]

• Release Date: H2 2026
• Next-gen APU refresh of the Ryzen AI Max 400 series #
• 16 cores / 32 threads, Zen 5, boost up to 5.2 GHz #
• Radeon 8065S iGPU: 40 RDNA 3.5 CUs at 3.0 GHz #
• Up to 192 GB LPDDR5X memory (up from 128 GB on Strix Halo) #
• ~4% multicore and ~3% single-core improvement over Strix Halo #

AMD Ryzen 9 9955HX3D

• Release Date: 2025 #
• Laptop CPU with 3D V-Cache #
• 64 MB L3 #
• 16 Zen 5 cores up to 5.4 GHz #
• 55 W to 75 W power limit #

AMD Zen 5c

• Release Date: Unknown
• 16 cores per CCD, in a single CCX that shares 32 MB L3 cache #
• Produced on a more advanced 3 nm node than Zen 5 #

AMD Zen 6 [updated]

• Release Date: Late 2025, early 2026 #
• Could be pushed back to H2 2026 #
• Codename: Morpheus #
• Codename: Sound Wave #
• Codename: Medusa Point (laptop) #
• Medusa Point uses soldered BGA, similar in size and Z-Height as Strix Point #
• Medusa Halo: 24 cores + 48 RDNA 5 CUs #
• Medusa Halo uses LPDDR6 memory #
• Another leak suggests bigger footprint BGA FP10 with 25 x 42.5 mm #
• Codename: Olympic Ridge (desktop) #
• Olympic Ridge supports Socket AM5 #
• October 2025 another confirmation that Zen 6 Olympic Ridge runs on AM5 #
• Gator Range for gaming laptops 55 W+ #
• Gator Range in 2027 #
• Bumblebee for value #
• 10% IPC increase over Zen 5 #
• Not sure if one CCX or two 16-core CCX's #
• Server codename: Venice #
• EPYC uses Socket SP7 #
• CCDs built using TSMC N2P process #
• Medusa point uses N2P compute tile + N3P I/O tile #
• 12 Zen 6 cores per CCD, in a single CCX, sharing an L3 cache of 48 MB #
• Another leak suggests 32-core CCD #
• Up to eight CCDs per EPYC CPU #
• 128 MB L3 per CCD #
• Medusa Point laptops will use RDNA 4 iGPU and an updated NPU in the IO die #
• Another leak suggests RDNA 3.5 iGPU GFX1153 for Medusa and RDNA 4 for Olympic #
• A newer leak suggests RDNA 4m iGPU GFX1170 #
• Could possibly introduce low power island CCX with Zen 6c #
• Zen 6c CCD will have 2 MB L3 cache #
• iGPU has 16 CUs #
• 3D V-Cache works the same as on Zen 5 #
• IO die is expected to be built using Samsung 4LPP # #
• Could also be built using TSMC N5 or N4P #
• Another leak suggests TSMC 2 nm for CCDs and 3 nm for IOD #
• Higher memory speeds supported at 1:1, over 10 GT/s with 1:2 # #
• 16- channel memory (SP7), 12-channel memory (SP8) #
• EPYC SP7: 600 W, SP8: 350-400 W #
• Will be supported on motherboards with 32 MB and 64 MB BIOS chips #
• CUDIMM support #
• New instructions: AVX512_BMM, AVX512_FP16, AVX_NE_CONVERT, AVX_IFMA, and AVX_VNNI_INT8 #
• OpenSIL support in 2026 #
• Medusa Point ES spotted on Geekbench: 10 cores, 32 MB L3 #
• Medusa Point ES matches Strix Point performance at half the clock speed #
• Additional RDNA 4m iGPU targets: GFX1171 and GFX1172 #
• RDNA 4m is adapted RDNA 3.5 with INT8/FP8 for FSR 4 support #
• AMD plans to use RDNA 3.5 / RDNA 4m iGPU through 2029 #
• Zen 6 PQOS ISA extensions detailed: GLBE, GLSBE, PLZA #
• X970E chipset confirmed: reuses Promontory 21 silicon from ASMedia, new 4 nm client I/O die with native CUDIMM and CAMM support #
• EXPO 1.2 launched with CUDIMM profiles; full CUDIMM support requires Zen 6 #
• EPYC "Verano" confirmed as Zen 6 (not Zen 7 as previously assumed), specialized for AI infrastructure #
• EPYC "Venice" Zen 6c up to 256 cores / 512 threads; regular Zen 6 up to 96 cores / 192 threads #
• Meta confirmed as lead customer for Venice and Verano EPYC CPUs #

AMD Zen 7 [updated]

• Release Date: 2027 #
• "Verano" originally assumed to be Zen 7, but now confirmed as Zen 6 specialized for AI #
• Zen 7 server codename and details not yet known
• Retains Socket SP7 infrastructure compatibility #

AMD Socket AM6

• Release Date: 2030 #
• Number of pins increased to 2100 #
• Increased power delivery capability, up to 200 W #
• PCIe 6.0 support #
• Possibly more PCIe lanes #
• Same physical size as AM5, coolers will be compatible #
• Expected to launch with Zen 7 #

AMD Ryzen 7 9700 X3D

• This made rounds on Reddit in November 2025 #
• Turned out it's a spoofed result and no such SKU exists #

Intel Diamond Rapids [updated]

• Release Date: 2026 #
• Branded as "Xeon 7" #
• Up to 192 P-Cores, split across four 48-core tiles
• Two SKU ranges: one uses 8-channel DDR5, the other 16-channel DDR5 #
• As of Nov 2025 the 8-channel SKUs have been canceled #
• MRDIMM Gen 2 support, 12,800 MT/s #
• Panther Cove cores #
• 500 W per socket #
• Platform: Oak Stream #
• 18A process #
• Intel APX support #
• Native support for TF32 and FP8 #
• LGA 9324 #
• Custom Xeons for NVIDIA with NVLink integration, for use in NVIDIA SuperPODs #

Intel Jaguar Shores

• Release Date: Mid-2026 #
• AI accelerator #
• Successor to Falcon Shores #
• Uses HBM4 memory #

Intel Nova Lake [updated]

• Release Date: Q3 2026 # #
• Engineering samples ready as of Feb 2025 #
• Successor to Arrow Lake
• Core Ultra 300 Series #
• New P-Core "Coyote Cove" #
• Other leak: 16 Coyote Cove P-Cores and 32 Arctic Wolf E-Cores and 4 LPE cores #
• Also considering 28-core (8P + 16E + 4LPE), and 16-core (4P + 8E + 4LPE) SKUs #
• Up to 52 cores # #
• ES: Running 52 cores at 4.8 GHz #
• NVL-SK: 2x (8P+16E), NVL-HX: 1x (8P+16E), NVL-S/NVL-H: 4P+8E, NVL-U: 4P+OE #
• Nova Lake AX: 8P, 16E, 4LPE, bigger iGPU with 384 EUs, LPDDR5X #
• Nova Lake HX: BGA2540 #
• Core Ultra 9: 16P, 32E, 4LP, 144 MB L3, 150 W #
• A more recent leak suggests 175 W power limit for the top SKUs #
• Core Ultra 7: 14P, 24E, 4LP, 120 MB L3, 150 W #
• Core Ultra 5 K and KF: 8P, 16E, 4LP, 72 MB L3, 125 W #
• Core Ultra 5 non-K Med: 8P, 12E, 4LP, 33 MB L3, 125 W #
• Core Ultra 5 non-K Value: 6P, 8E, 4LP, 24 MB L3, 65 W #
• Core Ultra 3 Med: 4P, 8E, 4LP, 18 MB L3, 65 W #
• Core Ultra 3 Entry: 4P, 4E, 4LP, 12 MB L3, 65 W #
• Possibly 4-core variant for low power laptops #
• Unlike Lunar Lake, no on-package memory #
• Uses TSMC 2 nanometer process for the CPU tile # #
• Should be "quite a jump from Arrow Lake (ARL) in terms of MT performance" #
• Intel bLLC could be their X3D equivalent, offering bigger L3 cache for gaming performance #
• bLLC CPU has up to 14 P-Cores #
• Socket LGA1954 #
• Older coolers are compatible # #
• Also using Intel 14 A #
• DDR5 memory #
• Default DDR5 speed is 8000 MT/s #
• Chipsets: B960 #
• PCI Express 6.0 #
• New Gen 6 NPU, newer than Panther Lake #
• 74 TOPS NPU #
• AVX 10.2 and APX officially confirmed #
• Xe3P iGPU # #
• RT support not available on all iGPU models #
• New NPU with over 100 TOPS IN8 #
• Compute tile: 110 mm² #
• bLLC tile: 150 mm² #
• Up to 700 W power with power limits disabled #
• Nova Lake-HX mobile: top config 8P+16E+4LPE, perf segment 6P+8E+4LPE #
• P-cores: Coyote Cove; E-cores: Arctic Wolf #
• Nova Lake-HX iGPU: Xe4 "Druid" with 2 Xe cores (minimal, designed for dGPU pairing) #
• Desktop iGPU confirmed as Xe3, display/media engine from Xe3P "Crescent Island" #
• Nova Lake-S desktop uses 2L-ILM socket mechanism for improved cooler contact #
• Desktop APU variant with 12 Xe3P cores being developed (4P+8E+4LPE config) #
• Nova Lake-AX (48 Xe3 cores) variant appears on hold #
• Desktop core configs leaked: from 4P+0E+4LPE up to dual-die 16P+32E+4LPE #
• bLLC (big last-level cache): Intel's answer to AMD 3D V-Cache #
• NPU6 in all SKUs; Thunderbolt 5 / USB4 V2 support #
• LGA1954 intended to last through end of decade #
• Z970 chipset will absorb much of the current B860 segment, becoming the primary mainstream chipset #
• Intel plans to expand overclocking support to budget CPU SKUs, possibly starting with Nova Lake #

Intel Bartlett Lake for Gaming

• Release Date: Unknown #
• CPU with 12 P-Cores #
• Bartlett Lake is already out for edge and networking applications, could come to gaming segment #
• Uses Socket LGA1700 #
• No E-Cores #
• Might be focused on OEM and embedded markets, not DIY retail #
• Top Bartlett Lake CPU available for sales as of March 2026 #
• Won't run on consumer motherboards #
• Modder got Bartlett Lake to run on consumer Z790 motherboard via BIOS mod #
• Core 9 273PQE booted Windows 11 on Z790 #

Intel Beast Lake

• Release Date: 2026 or 2027 #
• Successor to Arrow Lake #
• Uses Royal Core 1.1 P-Core architecture #

Intel Razer Lake [updated]

• Release Date: Unknown #
• Intel Core Ultra 400 Series #
• "Razor Lake-AX" variant to feature up to 32 Xe3 iGPU cores (~162 mm² GPU die), BGA-4326 package #
• On-package LPDDR5X/LPDDR6 memory returning with Razor Lake-AX #
• Original "Nova Lake-AX" plan with 48 Xe3 cores shelved; "AX" suffix moves to Razor Lake instead #
• Expected 2027 #

Intel Serpent Lake [added]

• Release Date: Unknown
• First Intel x86 SoC with integrated NVIDIA GeForce RTX GPU #
• Joint Intel-NVIDIA collaboration chip, similar concept to "Kaby Lake G" with AMD #
• Intel CEO Lip-Bu Tan confirmed ongoing product development #

Intel Arrow Lake "KS"

• Release Date: 2025 at least #
• Haven't heard from that for a long time, so might be canceled
• Could be called Core Ultra 9 295K #

Intel Grand Ridge

• Release Date: Unknown, could be canceled
• Produced on 7 nm HLL+ process
• Successor to Atom "Snow Ridge"
• 24 cores across 6 clusters with 4 cores each
• 4 MB L2 per cluster, plus L3 cache
• Uses Gracemont CPU core
• Dual-channel DDR5
• PCI Express Gen 4 with 16 lanes

Intel Twin Lake

• Release Date: Unknown #
• Successor to "Alder Lake N" #
• E-Cores only, using "Skymont" architecture #

Intel Griffin Cove

• Codename for new P-Core #
• Great-grandchild of Lion Cove #

NVIDIA N1 / N1X Arm CPUs for Desktop and Mobile

• Release Date: Delayed to Late 2026 #
• NVIDIA plans to build Arm processors for use in desktop computers #
• Will be used on upcoming Windows on Arm laptops #
• Windows 11 26H1 adds support for NVIDIA N1 and N1x #
• Codename N1 and N1X, GB10 #
• GB10 is the base design for N1 #
• SoC with 128 GB LPDDR5X and 1 to 4 TB SSD #
• 20 Arm cores: 10x Cortex X925, 10x Cortex A725 #
• TSMC 3 nanometer #
• LPDDR5X-9400 with 256-bit #
• 48 iGPU SMs #
• Microsoft Windows operating system is supported #
• 180-200 AI TOPS #
• Targets high-end segment #
• Volume: 3 million units #
• Partnered with MediaTek #
• Uses Blackwell GPU IP #
• ES: 2.8 GHz #
• Up to 3.9 GHz #
• Furmark 1.39 Donut test: 4286 points or 71 FPS at 720p (roughly half of RTX 5060)
• Geekbench OpenCL: 46361 points
• New Dell laptop listed with N1X ES2 SoC #
• N1 SoC surfaced on laptop motherboard with 128 GB LPDDR5X at 8,533 MT/s #
• Up to 6,144 CUDA cores in higher-end N1X form #
• OEM partners Dell and Lenovo confirmed #
• Launch expected around Computex 2026 #

Zhaoxin CPUs

• Release Date: Unknown #
• KH-50000: 96 cores, 2.2 to 3.0 GHz, SMT support unknown. 384 MB L3, 12-channel DDR5 memory, 128 lanes PCIe 5.0, up to 4 sockets #
• KX7000N: adds NPU, core count higher than eight, PCIe 5.0 #
• 12 Compute dies with a large central IO die #
• 12-channel DDR5 support #
• 128 lanes of PCIe 5 + 16 lanes Gen 4 #

Graphics / GPUs

NVIDIA GeForce RTX 5050 9 GB [updated]

• Release Date: 2026, possibly Computex # #
• 9 GB GDDR7 memory, 128 bit, 20 Gbps #
• Uses 3 memory chips with 3 GB capacity each #
• 130 W TDP (same as existing RTX 5050) #
• Uses GB206 die instead of GB207 #
• 2560 CUDA cores (same) #
• Transition from 8 GB to 9 GB model on pause due to reintroduction of GeForce RTX 3060 12 GB #

NVIDIA GeForce RTX 3060 Samsung 8 nm [updated]

• Release Date: Mid-March 2026 #
• GPU built using Samsung 8 nm DUV, to not use up capacity at TSMC #
• Unknown whether the new model is 12 GB, too, could be 8 GB with 128-bit bus #
• RTX 3060 12 GB returns in June 2026 #
• 192-bit bus, 12 GB GDDR6 confirmed #
• RTX 3060 chosen over RTX 4060 to preserve TSMC 5 nm capacity for Blackwell #
• Return confirmed for June with AIC partners ASUS, MSI, Colorful, and GALAX #

NVIDIA GeForce RTX 5060 / 5060 Ti 9 GB

• Release Date: May-June 2026, possibly Computex #
• 9 GB GDDR7 using three 3 GB memory chips #
• 96-bit bus (down from 128-bit), reduced bandwidth #
• RTX 5060 Ti 8 GB supply paused in late April for transition #

NVIDIA GeForce RTX 60-series (Rubin) [updated]

• Release Date: Unknown
• Based on "Rubin" graphics architecture #
• TSMC 3 nm FinFET variant #
• Chip naming: GR202 (flagship), GR203, GR205 #
• 6th Gen Tensor cores, 5th Gen RT cores #
• 100% RT / path tracing performance increase over RTX 50-series #
• 30-35% raster performance gains SKU-to-SKU #
• Clock speeds: high 2 GHz to low 3 GHz #
• RTX 6090: GR202, 192 SM, 512-bit GDDR7, 32 GB #
• RTX 6080: GR203, 320-bit GDDR7, 20 GB, 25%+ bandwidth increase over RTX 5080 #
• RTX 6070: GR205, 256-bit GDDR7, 16 GB, 33%+ bandwidth increase over RTX 5070 #
• AIC partner Palit confirms next-gen GALAX HOF and KFA2 variants already in development #

NVIDIA GeForce RTX 5080 24 GB

• Release Date: Unknown #
• 24 GB VRAM instead of 16 GB #
• Using 3 GB GDDR7 memory chips #
• Could be a typo by MSI #
• Could also be held back for RTX 5080 SUPER #

NVIDIA GeForce RTX 5080 Super, 5070 Ti Super, 5070 Super

• Release Date: Not before 2027 #
• Could be canceled due to GDDR7 shortage #
• Not canceled, but Q3 2026 #
• Newer leak: 2027 at best #
• Older leak: Christmas 2025 #
• Using 24 Gbit (3 GB) GDDR7 memory chips #
• RTX 5080 Super: 24 GB GDDR7, 32 Gbps, 256-bit, 84 SMs, 10,752 cores, 415 W #
• RTX 5070 Ti Super: 24 GB GDDR7, 28 Gbps, 256-bit, 70 SMs, 8,960 cores, 350 W # #
• RTX 5070 Super: 18 GB GDDR7, 28 Gbps, 192-bit, 50 SMs, 6,400 cores, 275 W # #

NVIDIA GeForce RTX TITAN Blackwell

• Release Date: Unknown #
• Another leak suggests late 2026 #
• GB202-200-A1 GPU #
• Could use the full GB202 GPU #
• 24,576 CUDA cores, 768 Tensor cores, 192 RT cores, 768 TMUs, and 192 ROPs, besides 88 MB of L2 cache #
• 512-bit GDDR7 memory interface #
• 32 Gbps memory speeds #
• Two 12V-2x6 power connectors #

AMD Radeon RX 9040

• Release Date: Unknown #

AMD Radeon RX 9050 [added]

• Release Date: Unknown
• 8 GB GDDR6, Navi 44 GPU (same die as RX 9060 but down-clocked) #
• 2048 stream processors (more than RX 9060's 1792 but lower clocks) #
• 1920 MHz game clock / 2600 MHz boost, PCIe 5 x16, HDMI 2.1b + dual DP 2.1a #
• Specs are preliminary; launch not imminent #

Intel High-End Battlemage / Arc B770

• Release Date: Q4 2025 #
• Uses BMG-G31 GPU #
• The lower end of the stack was launched in late 2024/2025 (Arc B580/B570) #
• 24 to 32 Xe2 compute units #
• Rumored that these were canceled in 2024 #
• 24 GB VRAM model based on BMG-G21, same as B580 #
• Another leak suggests 16 GB VRAM #
• Could be called B750, B770 and B780 #
• Support was added to AIDA64 in June #
• Leaked driver supports 3x Pro GPU configs and a single consumer GPU #
• Latest leak: 32 Xe2 + 16 GB GDDR6 256-bit #
• Arc Pro B70 has been released with this GPU. B70: 32 Xe2 cores (4,096 FP32), 32 GB GDDR6, 256-bit bus, B65: 20 Xe2 cores (2,560 FP32), 32 GB GDDR6 #
• Possibly 300 W TDP #
• Arc Pro B70 launched March 25 at $949.99, retail April 24 # #
• Consumer Arc B770 gaming GPU status unclear with Xe3P skipping gaming #

NVIDIA Vera Rubin [updated]

• Release Date: 2026 #
• Six months ahead of schedule as of June 2025 #
• Successor to "Blackwell" #
• Named after the scientist Vera Rubin #
• Flagship GPU: R100, built on TSMC 3 nm EUV, chiplet design, CoWoS-L with HBM4 #
• Grace Rubin GR200 could be 3 nm #
• 8 stacks of HBM4 #
• NVLink 6 switches with 3600 GB/s #
• TSMC 3 nanometer N3P node #
• CoWoS-L packaging #
• Looks like Vera Rubin is actually a combination of CPU "Vera" and GPU "Rubin", for enterprise compute, not for consumers #
• VR200 samples shipped as of Feb 2026 #
• "Rubin Ultra" reportedly faces issues with CoWoS-L packaging (warping with 4 dies + 16 HBM4E) #
• TSMC exploring CoPoS alternative, pilot lines 2026, mass production late 2028-H1 2029 #
• Standard Rubin mass shipments set for summer 2026 #
• Samsung HBM4 mass-production sales for Vera Rubin started February 2026 #
• SK hynix 192 GB SOCAMM2 now in mass production for Vera Rubin #
• SK hynix exploring Intel EMIB 2.5D packaging as alternative to TSMC CoWoS for HBM #
• HBM4E initial samples going out to customers in Q2 2026 #

AMD Navi 4c

• Release Date: Possibly canceled #
• Embraces chiplet design even more #
• Separate dies for Shader Engines (SED) and Multimedia & IO (MID) #
• Shader Engine Dies could be built on 3 nanometer TSMC #
• Uses an active interposer (AID) #

AMD RDNA 5

• Release Date: 2026 #
• Clean sheet design #
• Might not even have "RDNA" branding #
• Possible return to high-end: could feature 96 CUs and 384-bit memory #
• Codenames: Alpha Trion, Ultra Magnus, Orion Pax #
• Spotted in code update for LLVM gfx1310 target #
• GFX1310 codename confirmed #
• Full Dual-Issue VALU pipeline for Wave32, simultaneous X and Y ALU lane issue #
• FP32 compute utilization significantly improved over RDNA 3/4 #
• FSR Diamond announced for Xbox Project Helix, likely RDNA 5 / UDNA exclusive #

AMD UDNA

• Release Date: Unknown #
• AMD is expected to unify their RDNA and CDNA architectures into a single architecture #
• Improvements to RT performance #
• Will be used in next-gen Xbox and PlayStation 6 #
• Possible return to high-end: could feature 96 CUs and 384-bit memory #
• Support for 80 Gbit/s HDMI 2.2 #
• Four die sizes #
• Biggest core will have 96 CU #
• FSR Diamond announced for Xbox Project Helix #
• FSR Diamond expected to include multi-frame generation and neural rendering #

Chinese Lisuan LX 7G106 GPU

• Release Date: June 18, 2026 #
• Chinese-made discrete GPU, TSMC 6 nm #
• 24 TFLOPS FP32, 192 TMUs, 96 ROPs #
• 12 GB GDDR6, 192-bit bus #
• DirectX 12 (no ray tracing), Vulkan 1.3, AV1 decode up to 8K #

Imagination PowerVR on Windows

• Release Date: Unknown
• Imagination D-Series PowerVR GPU running on Windows with DX11, DX12, Vulkan 1.4, OpenGL 4.6 #
• Chinese manufacturer Xiang Dixian has shipped Fuxi A0 card based on this architecture #

Intel Celestial Architecture

• Release Date: Late 2025 or early 2026 #
• Could also be released in 2025 #
• Confirmed "in development" as of Jan 2024 #
• IP design is baked #
• Discrete GPU architecture
• Successor to "Battlemage" architecture
• Also called "Xe3 HPG"
• dGPU might be based on Xe3P instead of Xe3 #
• Fabricated on TSMC N3X (3 nm) # #
• Could also be fabricated using Intel in-house process #
• Targets "Ultra Enthusiast" segment
• 8192 shaders, 2x that of A770 #
• "Crescent Island" Xe3P will skip Arc gaming GPUs, focus on data center and workstations #
• No consumer discrete gaming GPU planned for Xe3P generation #
• Workstation "Crescent Island" GPUs with 160 GB LPDDR5X #

Intel Xe Next

• Release Date: 2026 or 2027 #
• Successor to Xe3P #
• Dedicated GPU #
• Likely manufacturing mix: Intel fabs + TSMC #
• HBM4 memory (Hynix) #
• Rack-scale accelerator designs targeting NVIDIA and AMD in data center market #
• Higher compute density, wider vector/matrix units, larger cache #

Intel Druid Architecture

• Release Date: Not before 2027
• Discrete GPU architecture
• Successor to "Celestial" architecture
• Also called "Xe Next HPG"

NVIDIA DLSS 5 [updated]

• Release Date: Fall 2026 #
• Real-time neural rendering that augments game assets with AI-generated lighting and materials #
• Takes 2D frame and motion vectors as input #
• Developer controls for intensity, color grading, and object masking #
• Supported by Bethesda, Capcom, Ubisoft, Warner Bros, Tencent #
• Community reception mixed: 58% of gamers say AI should not alter games, 28% awaiting real-world results #

Next-Gen DirectX Ray Tracing (DXR 2)

• Release Date: Spec published March 2026, hardware support TBD #
• Microsoft published DXR 2 functional spec #
• Clustered geometry for bulk triangle handling #
• Partitioned TLAS for independent scene graph updates #
• GPU-driven acceleration structure operations, bypassing CPU #

Chipsets

Intel Z990

• Release Date: Late 2026 (Nova Lake-S platform) #
• Flagship enthusiast chipset #
• DMI: Gen 5 x4 (128 Gbps per direction) #
• PCIe (chipset): 12× Gen 5 + 12× Gen 4 #
• CPU PEG: PCIe 5.0 x16 (x16 or x8/x8) #
• CPU NVMe: 2× M.2 Gen 5 supported #
• USB4 / TB4: 2× 40 Gbps from CPU #
• CPU OC: Multiplier + BCLK supported #

Intel Z970

• Release Date: Late 2026 (Nova Lake-S platform) #
• Enthusiast chipset below Z990 #
• Shares smaller PCH with B960 #
• DMI: Gen 5 x2 (64 Gbps per direction) #
• PCIe (chipset): 14× Gen 4 #
• CPU PEG: 1× PCIe 5.0 x16 #
• CPU NVMe: 1× M.2 Gen 5 x4 #
• USB4 / TB4: 1× 40 Gbps from CPU #
• CPU OC: Multiplier supported #

Intel B960

• Release Date: Late 2026 (Nova Lake-S platform) #
• Mainstream chipset #
• Shares smaller PCH with Z970 #
• DMI: Gen 5 x2 (64 Gbps per direction) #
• PCIe (chipset): 14× Gen 4 #
• PCIe 5.0 (chipset): None #
• CPU PEG: 1× PCIe 5.0 x16 #
• CPU NVMe: 1× M.2 Gen 5 x4 #
• USB4 / TB4: 1× 40 Gbps from CPU #
• CPU OC: Not supported #

Intel Q970

• Release Date: Late 2026 (Nova Lake-S platform) #
• Commercial desktop chipset #
• DMI: Gen 5 x4 (128 Gbps per direction) #
• PCIe (chipset): 8× Gen 5 + 12× Gen 4 #
• USB4 / TB4: 2× 40 Gbps from CPU #
• CPU OC: Not supported #
• Features: Intel vPro support #

Intel W980

• Release Date: Late 2026 (Nova Lake-S platform) #
• Workstation chipset for Xeon W #
• DMI: Gen 5 x4 (128 Gbps per direction) #
• PCIe (chipset): 12× Gen 5 + 12× Gen 4 #
• USB4 / TB4: 2× 40 Gbps from CPU #
• CPU OC: Not supported #
• Features: Intel vPro support #

Memory

LPDDR5M Memory

• Release Date: Unknown #
• Developed by Hynix #
• More power efficient than LPDDR5X #
• 0.98 V #

DDR6 System Memory [updated]

• Release Date: 2027 #
• Platform Validation: #
• Server Deployments: 2027 #
• Initial Draft from JEDEC: 2024 #
• Version 1.0 spec: mid-2025 #
• Four channels per module (2x that of DDR5, 4x that of DDR4) #
• Each channel is 24-bit (32-bit previously)
• 64 banks #
• Speeds starting at DDR6-8800 up to DDR6-17600 in 1st generation #
• LPDDR6 starts at LPDDR6-10667 with 24-bit channel with 2x 12-bit sub-channels #
• Maximum LPDDR6 data rate is expected to be LPDDR6-14400 #
• Commercial shipments now targeted for 2028 (delayed from 2027) #
• 4×24-bit sub-channel architecture (differs from DDR5's 2×32-bit) #
• CAMM2 form factor expected for high speeds #
• SK hynix, Samsung, and Micron actively designing in labs #

LPDDR6 Memory [updated]

• Release Date: H1 2026 #
• Samsung: 12 nm process, 10.7 Gbps, 21% improved energy efficiency #
• Hynix: 10 nm process (1c), 10.7 Gbps, 14.4 Gbps later #
• Hynix expects 20% improvement to efficiency
• Speeds are expected to reach up to 14 Gbps #
• Uses Dynamic Voltage and Frequency Scaling (DVFS) to dynamically adjust frequency and bandwidth
• JEDEC previews LPDDR6 roadmap: x6 sub-channel enables up to 512 GB densities #
• LPDDR6 SOCAMM2 module standard in active development #
• LPDDR6 Processing-in-Memory (PIM) standard nearing completion #
• SK hynix shipping world's first LPDDR6 on 1c nm (6th-gen 10 nm) process #

LPDDR6X Memory

• Release Date: 2027 #
• Qualcomm has received samples from Samsung as of Feb 2026 #

GDDR6W Graphics Memory

• Release Date: Unknown
• Builds on Samsung's Fan-Out Wafer-Level Packaging (FOWLP) technology
• Mounts the silicon memory dies on a wafer instead of a PCB
• Up to 22 Gbps per pin
• With a 512 bit interface that would be 1.4 TB/s
• Up to 24,000 MT/s
• Could be renamed GDDR6+

HBM4 Memory [updated]

• Sampling Date: 2025 #
• As of Nov 2025: Samsung samples shipped #
• NVIDIA requests faster mass production #
• Mass production: 2026 # # #
• Samsung: Non-conductive film (NCF) assembly and hybrid copper bonding (HCB) #
• Micron shipped samples as of June 2025 #
• Micron: 12-Hi 36 GB, 2 TB/s #
• Micron in Sep 2025: 11 Gbit/s #
• Hynix tapeout in Q4 2024 #
• Hynix in March 2025: 12-layer HBM4 samples shipped with 36 GB capacity #
• Hynix in Sep 2025: 10 Gbps #
• 2048-bit interface #
• 6000 MT/s #
• Uses a copper layer as a conductor and oxide insulator instead of regular micro bumps #
• TSMC and Hynix have formed a joint venture to develop HBM4 #
• TSMC will use 12 nm and 5 nm to produce HBM4 #
• TSMC: 12-Hi (48 GB) and 16-Hi (64 GB) stacks #
• Expected to be used in AMD's MI450 #
• NVIDIA lowers HBM4 speeds for Vera Rubin VR200, because memory speeds not ready #
• Micron reportedly no longer in the HBM4 race #
• Micron in high-volume HBM4 production (36 GB 12-hi, >11 Gb/s, >2.8 TB/s) #
• Samsung HBM4 in mass production: 11.7 Gbps, 1c DRAM + 4 nm logic base die #
• Samsung HBM4 mass-production for NVIDIA Vera Rubin confirmed, started February 2026 #
• Samsung warns 2027 memory shortage expected to be even wider than 2026 #
• Samsung 18-day worker strike starting May 21 will impact HBM production lines, ~3-4% of global DRAM at risk #
• SK hynix exploring Intel EMIB packaging as alternative to TSMC CoWoS #
• Samsung collaborating with AMD on HBM4 supply for Instinct MI455X GPUs #

HBM4E Memory [updated]

• Mass production: 2026 #
• SK Hynix development #
• Puts memory controller at the bottom of the memory stack #
• Samsung targets 13 Gbps / 3.25 TB/s, double efficiency than HBM3e #
• Samsung redesigns power delivery to improve defect rate #
• Rambus IP is ready: up to 16 Gbps #
• Samsung plans 2 nm process for HBM4E base die #
• Samsung HBM4E previewed at GTC: 16 Gbps/pin, 4.0 TB/s, hybrid copper bonding for 16+ layers #
• TSMC plans 3 nm for custom HBM4E #
• Initial samples going out to customers in Q2 2026 #

HBM-PIM Memory

• Release Date: Unknown
• Stands for "processing-in-memory" #
• Adds computation functions to the memory stack #

HBM5 Memory

• Release Date: 2029
• 20hi stack #
• Possibly using of Hybrid Bonding Technology #
• Keeps 8 Gbps speed, but 4096 bit #
• Used by NVIDIA Feynman GPU #
• 400 to 500 GB of memory per package, 4,400 W of power #
• Intel: 16 compute dies and 24 HBM5 modules in a single package #

HBM6 Memory

• Release Date: 2032 #
• 16 Gbps #
• 4096 bit #
• up to 20 layers, up to 120 GB per stack at 120 W #
• Immersion cooling and bumpless copper-copper bonding #

HBM7 Memory

• Release Date: 2035 #
• 24 Gbps #
• 8192 bit #
• 192 GB per stack at 160 W #

HBM8 Memory

• Release Date: 2038 #
• 32 Gbps #
• 16384 bit #
• 64 TB/s, 200-240 GB per stack at 180 W #

Intel HB3DM Memory [added]

• Intel and SoftBank subsidiary Saimemory developing alternative to HBM #
• Z-Angle Memory (ZAM) technology: 9 layers (1 logic + 8 DRAM), hybrid bonding #
• ~5.3 TB/s per 10 GB module, over 2.5x HBM4 bandwidth #
• Limited by capacity (10 GB vs HBM4's 48 GB per stack) #
• Prototypes expected early 2028, commercial products 2029 #
• Presenting at VLSI 2026 in June #

Game Consoles

Sony PlayStation 6 [updated]

• Release Date: Unknown #
• Production: Q2 2027 #
• Could launch along a new portable gaming handheld #
• Less processing power than new Xbox #
• Codename: PS6 Orion #
• 2.5-3x raster perf of PS5, and 6-12x RT performance #
• 4K 120 FPS in most games #
• AMD RDNA 5 GPU with 52-54 CUs at 2.0-3.6 GHz #
• 34-40 TFLOPs of theoretical performance #
• Up to 30 GB GDDR7 memory #
• Analysts predict PS6 could cost up to $999 for top variant #
• Base model estimated ~$600 digital, ~$750 disc #
• Leaker claims PS6 won't be delayed, AMD actively validating Canis and Orion APUs #
• Sony confirms frame generation coming to PlayStation "at some point" #
• Upgraded PSSR uses INT8 FSR 4 implementation #
• Sony CEO Hiroki Totoki confirms price and launch date not yet decided due to DRAM pricing uncertainty #
• Portable PS6 also in development; developers already optimizing for its APU before dev kits ship #

Microsoft Xbox "Project Helix" [updated]

• Release Date: Unknown #
• Codename: Project Helix #
• New Xbox CEO Asha Sharma confirmed next-gen hardware is coming #
• Rumored to be a hybrid console/PC device #
• Reportedly plays both Xbox and PC games #
• Sharma states Project Helix will "lead in performance" #
• May be a response to Steam Deck/Steam Machine rise #
• More info possibly revealed at GDC (March 9-13) #
• AI integration expected but Sharma claims she "will not tolerate AI slop" #
• Speculation and skepticism surround Sharma's leadership direction #
• Dev kits shipping end of 2027, confirming 2027-2028 launch window #
• AMD SoC with FSR Diamond, RDNA 5 / UDNA graphics IP #
• Designed to play Xbox console and PC games #
• Backwards compatible with Xbox Series, Xbox One, and Xbox 360 games #
• Analysts predict pricing as high as $999 #
• Will use off-the-shelf AMD APU with RDNA 5 and Zen 6/6c cores, no custom silicon #
• Leaker claims 68 RDNA 5 CUs, 48 GB GDDR7, chiplet design, equivalent to $2-3,000 gaming PC #
• Xbox VP confirms 1st-party Xbox console, leaves door open for 3rd-party variants #
• No disc drive expected; "Positron" disc-to-digital entitlement program planned #
• Xbox Game Dev Update event featured Helix preview #

Valve Steam Machine [updated]

• Release Date: 2026 #
• OS: SteamOS, optimized for gaming with fast suspend/resume and cloud saves #
• Form factor: ~6-inch (~160 mm) cube #
• Over 6x the horsepower of Steam Deck #
• 4K gaming at 60 FPS with FSR 3 upscaling, ray tracing supported #
• AMD is backporting support for FSR 4, so this will likely support FSR 4, too #
• CPU: Semi-custom AMD Zen 4, 6 cores / 12 threads, up to 4.8 GHz, ~30 W TDP #
• GPU: Semi-custom AMD RDNA 3, 28 CUs at up to 2.45 GHz, ~110 W TDP (comparable to RX 7600M) #
• VRAM: 8 GB GDDR6 #
• RAM: 16 GB DDR5 (SODIMM, user-upgradeable) #
• Storage: 512 GB and 2 TB NVMe options, expandable via M.2 (2230/2280) and microSD #
• 4K gaming at 60 FPS with FSR #
• Connectivity: 2x2 Wi-Fi 6E, Bluetooth 5.3 with dedicated antenna #
• Built-in Steam Controller wireless adapter #
• I/O: 1x Gigabit Ethernet, 1x DisplayPort 1.4, 1x HDMI 2.0, 1x USB-C, 4x USB-A #
• Internal power supply (no external brick) #
• Promise: Whisper-quiet cooling under heavy load #
• Half-Life 3 could be a launch title #
• SteamOS 3.8 preview brings initial Steam Machine support #
• Steam Machine "Verified" ditches UI legibility requirements #
• "Steam Frame Verified" label introduced #
• Shipment manifest tips Steam Controller launch soon #
• Launch delayed due to DRAM crisis; uses on-package RAM which is more severely affected #
• 4 SKUs leaked: 512 GB base model to 2 TB top model #
• Reservation system planned (one per account) to combat scalping #
• Valve stocking US warehouses, suggesting launch approaching #

Valve Steam Deck 2 [updated]

• Release Date: 2028 #
• Uses off-the-shelf AMD APU instead of semi-custom #
• Likely Zen 6 cores with RDNA 5 GPU IP #
• DRAM / NAND shortages could cause delays #
• Valve developer confirms Steam Deck 2 still in active development #

Valve Steam Frame [added]

• Release Date: H1 2026, may launch before Steam Machine #
• Arm-based gaming/VR device powered by Qualcomm Snapdragon 8 Gen 3 #
• 256 GB or 1 TB storage options #
• Possible PSU-less variant with 21.6 Wh battery using USB-C PD charging #
• Less affected by DRAM shortage than Steam Machine (uses mobile RAM, not on-package) #
• Proton 11 with improved FEX ARM emulation for x86 game compatibility #
• Appeared on Qualcomm's device finder page #

Nintendo Switch 2 Updates [updated]

• Release Date: Launched 2025
• Production cut by 33% (6 M to 4 M units) due to softening US sales and memory costs #
• EU revision planned with user-replaceable battery for right-to-repair compliance #
• $50 price increase to $499 (US) / €499 (EU) on September 1, 2026 due to rising DRAM and BOM costs #
• Sales target lowered to 16.5 million units for FY2027 (down 16.9%) #

Silicon Fabrication Tech

TSMC 2 nanometer

• Release Date: Q4-2024 Risk Production #
• Trial run in Q1 2025: very successful #
• Volume production: Q4 2025 # #
• Mar 2026: All capacity almost sold out until 2027 #
• June 2020: TSMC is accelerating R&D
• Sep 2020: fab construction has begun
• Capacity end of 2025: up to 80,000 wafers per month #
• 2026: 125,000 wafers per month #
• Aug 2025: In 2026, two plants expected with 60,000 wafers per month #
• Oct 2025: First wafers produced at Fab 22 #
• Will use Gate-All-Around (GAA) technology
• Probable VVIP customer: Apple #
• 15+ customers secured #
• First batch fully reserved for Apple #
• Yield rate: 90% #
• Other customers: NVIDIA, AMD and Broadcom #
• "Unprecedented Demand" #
• Multi-bridge channel field effect transistor (MBCFET) architecture
• 10-15% speed improvement over N3 at same power, or 25-30% power at same speed
• Several process variants: N2, N2P and N2X
• Not using High-NA EUV #
• Nanosheet transistors

TSMC 1.6 nanometer

• Release Date: 2027 or early 2028 #
• Backside power delivery #
• Will be used by NVIDIA Feynman GPUs #

TSMC 1.4 nanometer [updated]

• Risk Trial Production: 2027 #
• Pilot Runs: 2027 #
• Mass Production: H2 2028 # #
• Ahead of schedule as of Apr 2025 #
• Fab construction begins as of Nov 2025 #
• Codename "A14" #
• Not using High-NA EUV # #
• Uses 0.33-NA EUV #
• 15% speed improvement at same power #
• 30% power reduction at the same speed #
• 20% increase in density #
• $49 billion single-site investment #
• Taichung Phase 2 site ahead of schedule; trial production possibly as early as Q3 2027 #
• Mass production now expected H2 2028 #

TSMC 1.3 nanometer [added]

• Codename "A13" #
• Direct shrink of A14, 6% area savings, fully backward compatible with A14 designs #
• Production scheduled for 2029 #

TSMC 1.2 nanometer [added]

• Codename "A12" #
• A14 platform enhancement with Super Power Rail backside power delivery for AI and HPC #
• Production scheduled for 2029 #
• N2U (2 nm enhancement): 3-4% speed gain or 8-10% power reduction from N2P, production 2028 #
• 14-reticle CoWoS (10 compute dies + 20 HBM stacks) slated for 2028, beyond 14 reticles in 2029 #

TSMC 1 nanometer

• Release Date: around 2030 #
• Fab construction: 2026 #
• Uses Semi-metal bismuth for contact electrodes #
• Chip plan planning has started as of Nov 2022 #
• Codename "A10" #
• Uses High-NA EUV #

Samsung 3 nanometer

• Mass Production: H1 2022
• "Initial production" started as of Jun 30th 2022
• Uses Gate All Around FET transistors (GAA), Multi-Bridge-Channel FET (MBCFET)
• 45% less power while delivering 23% more performance
• 35% less silicon space taken per transistor (vs. 7 nm)
• 16% less silicon space taken per transistor (vs. 5 nm)
• 2nd generation 3 nm expected in 2025, reduces power by 50%, improves perf by 30%, reduces area by 35%
• Samsung claims 60-70% yields as of May 2023 #
• In Jul 2023 Samsung claimed 60% yields, and points out that this is better than TSMC #
• According to a newer report, both Samsung and TSMC are struggling with yields for their 3 nm node #
• Trial run of second-generation 3 nm process starting in early 2024 #

Samsung 2 nanometer

• Mass production: Q4 2025 #
• Uses Multi-Bridge-Channel FET (MBCFETTM)
• Feb 2024: order received for AI chips #
• Possibly using backside power delivery #
• Efficiency improved by 25%, performance by 12%, area by 5% #
• Samsung's new Texas fab might be 2 nm #
• Capacity in S3 foundry: 7000 wafers per month #
• First product: Exynos 2600 flagship SoC #
• Test run got 40%+ yields #

Samsung 1.4 nanometer

• In planning as of Oct 2022
• Plant construction: Q2 2025 #
• Mass Production: 2027 or 2028 #
• Could be canceled as of Mar 2025 #
• GAA (gate-all-around)
• 2.5D/3D integration
• Micro-bumps

Samsung 1 nanometer

• Mass Production: 2029 #
• Samsung will try to match or beat TSMC with 1 nm time to market #

Intel 14A [updated]

• Release Date: 2027 #
• "Engaging with multiple customers" #
• "Off to a great start" #
• 14 Angstrom = 1.4 nanometer #
• 15% performance per watt over Intel 18A #
• 20% increase in transistor density #
• High-NA extreme ultraviolet (EUV) # #
• Also 14A-E process with additional 5% performance boost #
• 15-20% performance per watt over 18A #
• Uses ASML TWINSCAN EXE:5200B #
• Uses "Turbo Cells" to boost frequency and cut power #
• NVIDIA and AMD exploring use of 14A #
• Intel Foundry nears major customer wins: Apple, AMD, Google, NVIDIA weighing deals #
• 14A PDK v1.0 release is key catalyst for new contracts #
• Intel EMIB demonstrated 47 tiles in a single package #
• Tesla signed as first major 14A customer for Terafab AI chip complex #
• Apple to use Intel 14A for A21 iPhone SoCs, expected ~2028 #
• PDK at v0.5; customers awaiting v0.9 for design finalization #

Intel 10A

• Release Date: end of 2027 #
• 10 Angstrom = 1 nanometer #

SMIC 5 nanometer

• Release Date: 2025 #
• Difficult due to lack of readily available EUV equipment in China #
• 40-50% more expensive than TSMC #

Rapidus 2 nanometer

• Release Date: 2027 #
• New fab project based out of Japan #
• $1.7B received in Mar 2026 #
• Uses ASML EUV #
• Goal: 25,000 wafers per month #
• Could use glass panel packaging #

Rapidus 1.4 nanometer

• Release Date: Unknown #
• Plant construction in 2027 #

Elon Musk "Terafab" [updated]

• Release Date: Years from completion #
• $20 billion semiconductor manufacturing plant (Tesla / SpaceX / xAI joint venture) #
• Location: Austin, Texas #
• Intel Foundry joins project, providing silicon design and advanced packaging (EMIB) #
• Two chip families: efficient inference and space-hardened chips #
• Years from completion #
• First phase cost: $55 billion, could reach $119 billion total #

Other

Hynix HBF High-Bandwidth Flash

• Release Date: Unknown #
• New memory architecture that comes 3D NAND storage with HBM-like bandwidth #
• 16 BiCS8 dies stacked #
• 4 TB memory usable like VRAM #
• pSLC #
• Hynix and Sandisk working on standardization #

NVIDIA SOCAMM Memory [updated]

• Release Date: Unknown #
• Developed by NVIDIA #
• System On Chip Advanced Memory Module—SOCAMM #
• Adapts CAMM for higher memory density #
• 694 I/O pins vs 644 on LPCAMM and 260 on DRAM #
• LPDDR5X substrate integration #
• Partners: SK Hynix, Samsung, Micron #
• Micron 192 GB SOCAMM2 modules in high-volume production for Vera Rubin NVL72 #
• SK hynix 192 GB SOCAMM2 now in mass production on 1c nm (6th-gen 10 nm) LPDDR5X #
• Rambus unveiled first commercial SOCAMM2 server module chipset #

ASRock HUDIMM Memory [updated]

• Release Date: 2026 #
• DDR5 with single 40-bit sub-channel (half bandwidth and density at rated speeds) #
• Targets entry-level builds during DDR5 shortage #
• Can pair with regular UDIMMs for asymmetric configs #
• Also developed HSODIMM (half SO-DIMM) variant #
• Partnered with Team Group for manufacturing #
• Gigabyte rolled out BIOS support across all Intel 800/700/600 series motherboards #
• Supports mixed HUDIMM + standard UDIMM configurations (e.g. 8 GB HUDIMM + 16 GB UDIMM = 24 GB with 3 sub-channels) #

Toshiba/WD 5-Bit-per-Cell NAND Flash (PLC)

• Release Date: Delayed to 2025
• Stores an additional bit of information per cell (compared to QLC)
• 32 states per cell
• Will enable even cheaper SSDs, probably at a performance cost

Samsung Z-NAND

• Release Date: Unknown #
• Up to 15x performance of regular NAND and ~80% lower power use #
• Direct GPU/accelerator access #
• Could make persistent storage behave like fast memory #
• Competitor to Kioxia's XL-FLASH #

Toshiba XL-Flash

• Developed by Toshiba
• Uses existing SLC flash technology to improve latencies
• 1/10th the read latency of TLC
• Good for random IOPS and better QoS at shallow queue depth
• Can combine SLC and TLC/QLC for tiered, cost-optimized storage
• Intel Optane memory competitor
• 128 gigabit (Gb) die (in a 2-die, 4-die, 8-die package)
• 4 KB page size for more efficient operating system reads and writes
• 16-plane architecture for more efficient parallelism
• Fast page read and program times

Hynix 321-layer 3D NAND Flash

• Release Date: H1 2025 #
• Mass Production: August 2025 #
• Transfer rate increased from 164 MB/s to 194 MB/s #
• 1 Tb capacity with TLC #
• 20 Gbit/mm² #
• 41% more bit growth, 13% shorter read latency, 12% faster program performance, 10% better read power efficiency #
• 16 KB page size, 4 planes #
• QLC: 6 planes #
• QLC: Write performance improved by 56%, read performance improved by 18%, 23% better power #
• 2400 MT/s #
• Made from three stack of 107-layers each #
• QLC cSSDs now shipping, Dell first customer #

Hynix 400-layer 3D NAND Flash

• Release Date: 2025 Q4 #
• Uses Hybrid Bonding Technology #

Samsung 290 layer 3D NAND Flash

• Release Date: 2024 #
• Mass Production started of 1 Tbit TLC: Apr 2024 #
• 9th generation V-NAND #
• 11 nm class process #

Samsung 280-layer 3D NAND QLC Flash

• Release Date: H1 2026 #
• Density: 1 Tbit #
• Density: 28.5 Gb/mm² at 3.2 GB/s #

Samsung 430-layer 3D NAND Flash

• Release Date: 2026 #
• Uses Bonding Vertical Technology, so separate layers can be bonded together, to improve yields #
• Up to 60% density improvement #

Kioxia 1000-layer 3D NAND Flash

• Release Date: 2027 #
• QLC and PLC #

Samsung 1000-layer 3D NAND Flash

• Release Date: 2030 #
• Multi-BV NAND design #
• Stacks four wafers to overcome structural limits #

YMTC 294-layer 3D NAND Flash

• Shipping as of Jan 2025 #
• TLC #
• 232 active layers #
• Uses hybrid bonding #
• XTacking 4.0 #
• First SSD using the flash is from Zhitai #

PCI Express 6.0

• Release Date: 2023
• Hardware expected: 2024
• Spec version 1.0 published as of Jan 2022
• Spec version 0.9 published as of Oct 2021
• Spec version 0.5 published as of Feb 2020
• Spec version 0.7 published as of Nov 2020
• 64 GT/s raw bit rate, up to 256 GB/s with x16
• Rambus has controller IP ready as of Jan 2022
• Rambus has PHY and controller ready as of Oct 2022
• Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
• Maintains backwards compatibility with all previous generations of PCIe technology
• New physical layer with PAM4 (pulse amplitude modulation) signaling replacing NRZ (non-return to zero)

PCI Express 7.0

• Release Date: 2025 #
• Version 0.3 released as of Jun 2023 #
• Version 0.5 released as of Apr 2024 #
• Version 0.7 released as of Jan 2025 #
• Version 0.9 released as of Mar 2025 #
• Version 1.0 released as of Jun 2025 #
• Spec is work in process as of 2022
• 128 GT/s raw bit rate, up to 512 GB/s with x16 #
• PAM4 signaling #
• Improved power efficiency #
• Backwards compatible with all previous versions of PCIe #

PCI Express 8.0 [updated]

• Release Date: 2028 #
• Version 0.3 released as of Sep 2025 #
• 256 GT/s #
• Continues to use PAM4 signaling #
• Backwards compatible #
• Draft v0.5 released #
• Evaluating new connector technology; current copper connector may be a limiting factor at 256 GT/s #
• Targets 1 TB/s bidirectional bandwidth in x16 configuration #