According to the latest research from Morgan Stanley, one of the leading investment banks, we have learned that the defect rate for Intel's 14A node is currently reported at D0=0.5. This means that defects in Intel's 14A node production are occurring at a rate of only 0.5, indicating a limited amount of purely non-functional silicon produced during the long and challenging semiconductor manufacturing process. For Intel, this suggests that the 14A node is still in the early stages of ramping up. However, the previous claims that this node is currently surpassing the 18A node at a similar development and ramp time are indeed accurate. For example, Intel plans to target a defect rate of only 0.1 to 0.2 by the first quarter of 2027, when the company intends to start running internal test chips and initiate a slight ramp-up for its own products. This will be followed by risk production in 2028 and high-volume production in 2029.

Looking at Intel's current "Panther Lake" SoC, which integrates multiple smaller dies into a unified package, we observe that Intel has utilized its 18A node for the compute tile's production. This tile measures approximately 8.004 x 14.288 mm, resulting in a silicon area of 114.304 mm². If we take this die size and apply the current parameters of the 14A node, we can estimate that a similar die, with the same surface area but increased density and manufactured on the 14A node, would achieve a yield of 56.45% for designs of that scale. Naturally, the current 18A node is providing better yields due to high-volume manufacturing, but the initial statistics for 14A appear promising. This assumption is based on a die of that specific size, with that particular defect rate, using High-NA EUV half-field exposures in the production process. We believe this is the stage Intel's 14A node is currently at, with room for many improvements. While Morgan Stanley notes in their report that the yield is about 40% for a test chip, its size must be significantly larger than the assumed size of the "Panther Lake" compute tile.

For Intel, this means that once the node achieves a significant D0 defect rate improvement to 0.1 or 0.2, the yield for a die with an area of roughly 100 mm² would be 80-90%, depending on the exact design. Interestingly, this yield assumption only considers the Poisson yield model, though there are many others. We also need to consider the so-called parametric yield, which refers to the number of chips that meet the complete functional requirements set by the company. It's not just about whether the dies work at all, but whether they work fully as intended. This is a whole other topic, and it's unlikely we'll ever learn much about it, as such information is typically kept within Intel.

Finally, it's worth noting that Intel's 14A node is currently at the 0.5 PDK stage. Customers will finalize volume, design, and other requirements when the 0.9 PDK is released. Lip-Bu Tan expects this 0.9 PDK, which he refers to as a "holy grail," to be available in October of this year. In collaboration with ASML, Intel has completed acceptance testing at Intel Foundry for its 14A node to enhance wafer output. The TWINSCAN EXE:5200B is ASML's second version of High-NA EUV scanners, following the TWINSCAN EXE:5000, which Intel initially used for its 14A trial runs. Intel previously reported processing over 30,000 wafers in a single quarter, achieving simplified manufacturing by reducing the steps needed for a specific layer from 40 to fewer than 10, resulting in significantly faster cycle times.