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The LineShine comprises 13.79 million ARMv9 cores, spread across 20,480 nodes in a non-uniform memory access (NUMA) configuration. Each node contains two LX2 CPUs, with 304 cores and 32 GB of HBM memory. The CPU uses HBM for fast memory access, then offloads to system DDR memory, which has about 256 GB per CPU. The CPU is split across two dies, each divided into four NUMA domains. Each NUMA domain contains 38 cores running at 1.55 GHz and has 4 GB of HBM assigned to it. Four of these NUMA domains make up a die, and each die is assigned 128 GB of DDR memory. This is likely DDR5, but we haven't confirmed those details yet.
The system draws 42.2 MW of power and achieves an efficiency of 52.07 GigaFLOPS/Watt. It is the only Exascale system in the TOP500 list that uses CPU-only compute power. A similar design was employed by the Japanese Fugaku supercomputer, but that system managed only about half an ExaFLOP of sustained throughput. Finally, the TOP500 list has verified the performance claims of the LineShine supercomputer, marking the first time a Chinese HPC entry has reached the top of the TOP500 list, officially ranked and verified.
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