High radix, low latency and low power is what AI datacenters crave, the chipmaker says
COMPUTEX 2026 Marvell enjoyed a fillip from Nvidia chief Jensen Huang at Computex, who praised the firm as it unveiled the latest 102.4 Tbps switch silicon it has purpose-built for AI infrastructure.
The fabless semiconductor biz announced upcoming availability of its Teralynx T100 chip to coincide with the Taiwanese trade show, claiming that it needs 25 percent lower power than competitive solutions with lower latency for AI training and inference workloads.
But the firm is late to this party, as other vendors are already shipping their equivalent products, such as Broadcom’s Tomahawk 6 that launched last year, or Cisco’s Silicon One G300 announced earlier this year.
That didn’t stop Nvidia’s Huang from styling Marvell as the “next trillion-dollar company," and saying that its networking and connectivity chips are essential to datacenters where compute tasks are distributed across thousands of connected nodes.
According to Reuters, the chipmaker’s shares surged in value more than 24 percent in pre-market trading following Huang’s remarks. The rockstar CEO will no doubt be pleased, as his company invested $2 billion in Marvell earlier this year, at the same time as announcing a strategic partnership to connect the firm with Nvidia’s AI factory initiative.
Marvell has an estimated market capitalization of approximately $179 billion to $196 billion, so it has some way to go to get to that trillion-dollar mark, but perhaps it is hoping its new silicon will get it there.
As GPU racks approach 120 KW of power, a low-power switch enables datacenters to deploy larger numbers of accelerators within existing power envelopes, the firm says.
The Teralynx T100 is a monolithic device manufactured using a 3nm process technology, which eliminates unnecessary legacy elements that otherwise increase power and die area. Because of this, it comes in at under 1000 W typical power, which sounds like an awful lot to us, but it is claimed to be 25 percent lower than rivals.
For scale-out deployments, the switch chip supports up to a 512-port radix, enabling operators to consolidate network tiers and reduce latency across large AI training clusters. The more ports there are in a switch, the higher the radix, and the fewer of them are needed for a given number of endpoints, as The Register previously detailed, cutting latency by flattening the hierarchy.
However, for scale-up deployments, Marvell says the product’s programmable pipeline architecture supports a variety of interconnect standards and emerging scale-up fabric protocols. These include the Ethernet Scale-Up Networking (ESUN) protocol, the latest Ultra Ethernet Consortium (UEC) requirements and evolving AI Ethernet fabrics.
“The Teralynx T100 was purpose-built for AI - designed without the legacy baggage that inflates power, and engineered to deliver the deterministic performance and efficiency required to scale next-generation datacenter infrastructure,” Marvell’s Data Center Switch Business Unit VP Rishi Chugh remarked.
“As AI workloads evolve and scale exponentially, hyperscalers require network architectures that optimize latency, power and scalability simultaneously,” he added.
The Teralynx T100 switch will begin sampling to customers this quarter. It will be available in multiple package configurations, including ball grid array (BGA), co-packaged copper (CPC) and co-packaged optics (CPO) implementations. ®