1. The Macro Level (Facility)

Path: Grid → Substation → Switchgear → UPS

To train Large Language Models, data centers act as a single, unified supercomputer. When a training sequence initiates, the facility experiences a massive, synchronized demand for power.

The journey begins at the utility grid, carrying raw, unconditioned power at extreme voltages (110kV+). An on-site Substation steps this down to a medium voltage (typically 11kV to 35kV).

The most critical facility-level component is the Uninterruptible Power Supply (UPS). If the grid fluctuates or fails, diesel or gas generators take several seconds to boot. The UPS utilizes massive battery arrays to bridge this gap, ensuring the AI clusters never lose power.

+------------------+     +------------------+     +------------------+     +------------------+
|   Utility Grid   | --> |    Substation    | --> |   UPS & Genset   | --> |     Room PDU     |
|   > 110 kV AC    |     |   11-35 kV AC    |     |     480 V AC     |     |     415 V AC     |
+------------------+     +------------------+     +------------------+     +------------------+
                                                                                          |
                                                                                          v
                         +------------------+     +------------------+     +------------------+
                         |   AI GPU Core    | <-- |    VRM / PoL     | <-- |   Power Shelf    |
                         | 0.7 V / 2,083 A  |     |  48 V -> 0.7 V   |     |     48 V DC      |
                         +------------------+     +------------------+     +------------------+

Key Players: Companies like Schneider Electric, Eaton, and ABB dominate this infrastructure. Semiconductor companies (e.g., Infineon, Wolfspeed) provide the Silicon Carbide (SiC) switches inside the UPS, with some modern UPS products advertising up to ~99% efficiency.

2. The Distribution Level

Path: UPS → Floor PDUs → Busways → Rack

Once power is conditioned by the UPS, it is distributed across the data center floor. It travels through large transformers inside floor-level Power Distribution Units (PDUs), which step the voltage down to 415V or 240V AC.

This power is transported down the aisles of server racks via overhead or underfloor copper bars known as Busways. Because AI racks consume significantly more power than traditional web-hosting racks (up to 120kW per rack compared to a traditional 10kW), these busways must carry immense current.

Traditional mechanical circuit breakers are being replaced by Solid-State Circuit Breakers (SSCBs) that can cut power in microseconds to prevent catastrophic arc flashes. AI datacenter operators are willing to significantly increase their spending for these components, because a single power malfunction in their facility can be incredibly expensive.

3. The Rack Level (48V Pivot)

Path: Rack PDUs → Power Shelves

This stage represents the most significant architectural pivot in modern AI infrastructure. For decades, traditional servers operated on a 12-Volt DC backplane. However, the sheer power density of AI GPUs renders 12V economically and physically highly impractical due to transmission limits.

To facilitate this, racks now feature Power Shelves—centralized banks of power supply units (PSUs). These shelves take the incoming AC power and convert it into highly stable 48V DC. Inside these PSUs, Gallium Nitride (GaN) and Superjunction MOSFETs switch at incredibly high frequencies, allowing power supplies to remain compact while delivering Titanium-grade efficiency. NVIDIA’s NVL72 architecture has emerged as the de-facto reference for 120 kW liquid-cooled racks at hyperscale,[1] anchoring the industry’s transition to the 48 V DC backplane.

4. The Board/Chip Level

Path: 48V DC → VRMs → AI Silicon Core

The final stage is one of the the most demanding power engineering environment in the world. The 48V DC power arrives at the motherboard and must be immediately stepped down to the exact voltage the silicon logic requires (usually between 0.6V and 0.8V).

This transition is handled by Point-of-Load (PoL) converters and Voltage Regulator Modules (VRMs). A single flagship AI GPU (like NVIDIA’s Blackwell) can consume over 1,200 Watts.[2] At 0.7 Volts, a single chip demands nearly 1,700 Amps of current.

Traditional Lateral Power Delivery (LPD) clusters VRMs around the silicon. To combat transient resistance, next-generation architectures are replacing this with Vertical Power Delivery (VPD), placing the VRMs directly underneath the GPU rather than next to it. Semiconductor companies supply the specialized smart power stages and digital controllers that orchestrate this rapid-fire energy delivery.

Conclusion

The AI buildout is inextricably linked to power infrastructure. As model sizes scale, the physical limit of computation is bound by our ability to efficiently convert 110,000 Volts from the grid into 0.7 Volts at the silicon core. The companies that master this conversion across the entire macro-to-micro value chain will be essential during the next era of high-performance computing.