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To address these challenges, we propose PoTAcc, an open-source end-to-end pipeline for accelerating and evaluating PoT-quantized DNNs on resource-constrained edge devices. PoTAcc enables seamless preparation and deployment of PoT-quantized models via TensorFlow Lite (TFLite) across heterogeneous platforms, including CPU-only systems and hybrid CPU-FPGA systems with custom accelerators. We design shift-based processing element (shift-PE) accelerators for three PoT quantization methods and implement them on two FPGA platforms. We evaluate accuracy, performance, energy efficiency, and resource utilization across a range of models, including CNNs and Transformer-based architectures. Results show that our CPU-accelerator design achieves up to 3.6x speedup and 78% energy reduction compared to CPU-only execution for PoT-quantized DNNs on PYNQ-Z2 and Kria boards. The code will be publicly released at this https URL
| Comments: | Accepted to IEEE Transactions on Circuits and Systems for Artificial Intelligence (TCASAI), 2026 |
| Subjects: | Hardware Architecture (cs.AR); Machine Learning (cs.LG); Performance (cs.PF) |
| Cite as: | arXiv:2605.06082 [cs.AR] |
| (or arXiv:2605.06082v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2605.06082 arXiv-issued DOI via DataCite (pending registration) |
From: José Cano [view email]
[v1]
Thu, 7 May 2026 12:03:08 UTC (2,891 KB)
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