Abstract:In modern computing units, division operations are generally slower than other arithmetic operations and require more resources, such as area and power, than multiplication. To reduce the delay, fast division algorithms use an initial approximation of the reciprocal of the divisor and iteratively approach the correct value, followed by multiplication with the dividend. The hardware architecture and choice of algorithm can significantly alter the overall performance of the division unit. This paper proposes a reduced-accuracy division method for the posit number system, which is an alternative to the traditional floating-point system. The proposed design uses a Look-Up Table (LUT) and a single subtraction operation to perform approximate divisor reciprocation by this http URL paper also presents a hardware architecture that combines multiplication and division units. The reciprocal calculation has been incorporated into the posit Decoder, a common unit required to perform any hardware operation with posits. Compared to existing hardware implementations of division, the proposed method requires significantly fewer operations at the cost of perfect rounding for division. The proposed architecture was simulated using the Cadence RTL v7.1 E2 compiler at the TSMC 90 nm process node and achieves a Power Delay Product (PDP) reduction of 78.8% compared to an existing design that performs exact division, while only 46.33% of the area is required. The experimental results also demonstrate the effectiveness of the proposed system in improving the efficiency of multiplication in posit-based systems.
| Subjects: | Hardware Architecture (cs.AR) |
| Cite as: | arXiv:2605.24665 [cs.AR] |
| (or arXiv:2605.24665v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2605.24665 arXiv-issued DOI via DataCite (pending registration) |
From: Aditya Anirudh Jonnalagadda [view email]
[v1]
Sat, 23 May 2026 17:07:17 UTC (777 KB)
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