Abstract:Many-core neuromorphic systems accelerate Spiking Neural Networks (SNNs), yet their packet-based spike communication can spend substantial traffic and energy repeatedly transmitting destination addresses. This overhead is amplified by the small payload of spike packets: in representative workloads, duplicate address transmissions account for up to 49% of the total traffic. This paper presents UniSpike, a hardware-software co-design that removes address redundancy by aggregating spikes destined for the same core into compact packets. UniSpike combines destination-centric spike scheduling, lightweight runtime packet assembly hardware, and destination-aware SNN partitioning. Across diverse SNN workloads, UniSpike reduces traffic by 1.93$\times$ on average, delivering 1.77$\times$ speedup and 1.50$\times$ energy efficiency improvement over state-of-the-art designs.
| Comments: | Accepted to the 63rd Design Automation Conference (DAC 2026) |
| Subjects: | Neural and Evolutionary Computing (cs.NE); Hardware Architecture (cs.AR) |
| Cite as: | arXiv:2605.23796 [cs.NE] |
| (or arXiv:2605.23796v1 [cs.NE] for this version) | |
| https://doi.org/10.48550/arXiv.2605.23796 arXiv-issued DOI via DataCite (pending registration) |
From: Xin Du [view email]
[v1]
Fri, 22 May 2026 15:57:55 UTC (853 KB)
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