Along with the many x86/x86_64 improvements and some ARM64 architecture improvements (albeit slowed down by the AI/LLM noise affecting the development pace), the RISC-V architecture changes were merged last week for the ongoing Linux 7.2 kernel development.

For those using the SiFive HiFive Premier P550 or other RISC-V boards using an Eswin SoC, the RISC-V default kernel configuration now enables Eswin SoC support. The RISC-V defconfig is updated to now include this Eswin SoC support with the developer motivation in wanting to ensure the default RISC-V kernel builds support the popular SiFive HiFive Premier P550 board.

RISC-V meets all the requirements for HAVE_BUILDTIME_MCOUNT_SORT and by setting it, the sort table is able to sort the __mcount_loc section at link time that in turn reduces kernel start-up overhead within the ftrace initialization path.

RISC-V for this next kernel version also has a number of code clean-ups, fixing a potential memory leak in the cacheinfo code, and various fixes.

The full list of RISC-V feature changes for Linux 7.2 can be found via this pull request.