May 21, 2026 – IBM’s quantum error correction team posted a 90-page preprint that does something no previous paper has attempted: concatenate an algebraic outer code over a high-rate quantum LDPC inner code and prove that the combination works at operationally relevant error rates.
The paper, “Concatenating Algebraic Codes over High-Rate Quantum LDPC Codes” by Adam Wills (MIT/IBM), Michael Beverland, Lev Bishop, Jay Gambetta, Patrick Rall, Vikesh Siddhu, and Andrew Cross, takes the [[144, 12, 12]] bivariate bicycle “gross” code (the same code at the heart of IBM’s modular bicycle architecture) and wraps it inside a quantum Reed-Solomon outer code. At 10-3 physical noise, the concatenated system reaches the teraquop regime (logical error rates around 10-14 to 10-13 per logical qubit-round), a threshold the standalone gross code could not reach. It does so with lower space overhead than the larger 288-qubit “two-gross” code, down to a logical error rate of 4.10 × 10-15.
For anyone tracking the engineering path to a CRQC, the bottom line: this result closes a gap in IBM’s fault-tolerance roadmap. The modular gross code architecture, built from small 144-qubit chips connected by inter-module couplers, can now access the error-rate regime needed for large-scale quantum algorithms. And the techniques are not restricted to IBM’s hardware. The core ideas (Galois qudits, quantum Reed-Solomon codes, list decoding for large alphabets) transfer to any high-rate quantum error correction scheme.
The central contribution of this paper is a reformulation of what it means for a high-rate code to fail.
IBM’s gross code encodes 12 logical qubits in 144 physical qubits. When errors accumulate on a gross code block, its 12 logical qubits do not fail independently; they fail in a highly correlated way. If you tried to protect each logical qubit separately with a standard outer code, you’d need the outer code to have distance 12 or higher to handle the worst case, which would destroy the encoding rate and defeat the purpose.
Wills et al. solve this by sacrificing one logical qubit (the “pivot”) for operations, then packaging the remaining 11 into a single Galois qudit of dimension 211 = 2,048. The mathematical machinery comes from finite field theory, where a set of s qubits can be treated as one qudit of dimension 2s with isomorphic Pauli and Clifford groups. A companion paper (arXiv:2605.18981) develops this formalism in detail.
Once each gross code block is a single qudit, the outer code only needs to count how many blocks have errors, not how the errors distribute within each block. A distance-d quantum Reed-Solomon code over 2,048-dimensional qudits can tolerate errors in up to ⌊(d−1)/2⌋ blocks, regardless of how catastrophically each individual block fails internally. Reed-Solomon codes are the optimal choice here: their parameters [[n, n − 2(d − 1), d]]2048 meet the quantum Singleton bound. They are information-theoretically optimal for any given distance.
Classical coding theory discovered this same design principle decades ago for handling “bursty” error channels in communications, storage, and optical media. Pack multiple bits into larger symbols and use algebraic codes designed for those symbols. The quantum version works just as well.
The most technically surprising finding in the paper concerns what happens to fault tolerance when your alphabet is large.
For syndrome extraction, the team develops a Shor-style error correction scheme adapted for Galois qudits. They prepare “qudit cat states” (the natural generalization of the familiar qubit cat state) and consume them to measure the outer code’s stabilizers. To protect against measurement errors, they measure an overcomplete basis of stabilizers and check consistency, using a “time-like” Reed-Solomon code to detect faults.
In standard qubit fault tolerance, a single data error during syndrome extraction can produce the wrong syndrome while keeping the round looking self-consistent. The concatenated code then fails at the same rate as the inner code. For qubits (alphabet size 2), there is no suppression; the scheme simply does not provide fault tolerance against this failure mode.
For qudits with alphabet size q = 2,048, the situation is qualitatively different. The probability of such a failure scales as roughly n(d − 1 − M)/(q − 1)M, where n is the code length, d is the distance, and M is the number of extra consistency checks. When q = 2,048 and M is even modestly large, this probability is exponentially suppressed. A single fault that would be fatal for a qubit code becomes negligible for a 2,048-dimensional qudit code.
The paper traces this effect to the list-decodable structure of Reed-Solomon codes over large alphabets. When errors occur randomly on high-dimensional qudits, the probability that they “line up” with an uncorrectable error pattern is very small, because there are 2,047 possible error values at each position and the uncorrectable patterns are a vanishing fraction. On a distance-6 code, for instance, a random weight-3 error is uncorrectable with probability roughly (n − 3)(n − 4)(n − 5) / 6(q − 1)2, which is tiny when q = 2,048 and n ≈ 30–80.
Wills et al. argue this is a different regime of fault tolerance from anything the qubit world has produced. Their phrasing is direct: “the theory of fault tolerance on qudits should be considered quite differently to that on qubits.” If that claim holds up under further scrutiny, the implications extend well beyond this specific construction. Any high-rate qLDPC code whose logical qubits can be packaged into large Galois qudits could benefit from the same algebraic protection.
The paper also addresses a problem every QEC scheme faces: you cannot simulate the probability of every possible logical error on a 12-logical-qubit code, because there are 412− 1 = 16,777,215 possible Pauli errors per block.
To handle this, the team introduces what they call “spacetime error mixing.” They treat the qudit-to-qubit mappings (how each qudit is decomposed into its constituent qubits) as a free parameter. By taking a uniformly random choice of these mappings, they show that, in expectation, the error distribution on each qudit becomes uniform. They can then bound the failure probability using only aggregate statistics they can measure (like the total logical error rate of an idling gross code), rather than the full error distribution they cannot.
This is a proof technique, not a protocol requirement. On real hardware with real-time decoding, you’d have access to more detailed information about your error distribution and could make a more targeted choice of mappings. The mixing argument guarantees that a good choice always exists, regardless of the actual error distribution, and that random search will find it quickly.
At uniform 10-3 physical error rate, a widely used benchmark that roughly corresponds to current superconducting hardware capabilities, the concatenated gross code achieves logical error rates in the 10-13 to 10-15 range per logical qubit-round, depending on outer code distance and system size. It delivers lower space overhead than the 288-qubit two-gross code (the next-larger code in the bivariate bicycle family) down to 4.10 × 10-15 per logical qubit-round. All results fit within a system of half a million physical qubits.
The space overhead curve smoothly fills the gap between the standalone gross code (which tops out around 10-9) and the two-gross code (which kicks in around 10-8 but requires a substantial jump in chip complexity). Engineers can tune the outer code distance from 3 through 9, with each distance optimal in a different error-rate regime. This smooth tunability is a practical advantage: the surface code scales continuously by increasing patch size, but qLDPC codes tend to come in discrete families with large jumps between them. Concatenation removes that constraint.
At 10-4 physical noise, the results are much stronger. The system reaches logical error rates below 10-20, and post-selection strategies (rejecting suspicious decoding instances) become highly effective at this lower noise level. Post-selection alone improves logical error rates by two to four orders of magnitude at the same space overhead.
Three limitations matter for assessing the practical significance.
First, this is a memory analysis, not a computation analysis. The paper is explicit about this: “Extending the present memory analysis to computation raises additional challenges; for example, in the explicit construction analysed here, the slow outer-code cycle would constrain the rate of computation.” A quantum memory that cannot compute is useful as a dense storage block within a larger architecture, but it is not a computer. The authors list extending to full computation as a primary future direction.
Second, the cat state preparation is slow. At 10-3 noise, the dominant error source is not gate errors but the gross codes sitting idle while cat states are assembled from the limited native gate set of the bicycle instructions. The paper’s Appendix C demonstrates a “morphing” idling circuit that could improve this bottleneck (the mean logical error rate per round drops from ~10-8.8 to ~4.4 × 10-11), but this circuit has not yet been fully validated and would require redesigned ancilla systems. The improvement is “anticipated,” not delivered.
Third, the concatenated gross code will not beat the 2D yoked surface codes from Gidney et al. (Nature Communications, May 2025) on raw space overhead. The paper acknowledges this directly: “improvements to the concatenated gross system are unlikely to render a 10× improvement in space overhead over the 2D yoked surface codes.” The comparison is more favorable against the 1D yoked layout, and the concatenated gross code has a practical access advantage. Its 1D layout makes reading and writing logical information easier than the 2D yoked surface codes, which the authors describe as “only usable for very cold storage.”
The past 18 months have produced a rapid compression of the QEC design space.
Google’s Gidney showed in May 2025 that RSA-2048 could be factored with under a million noisy qubits using yoked surface codes for dense memory storage, a 20× reduction from the 2019 estimate. That paper used the teraquop regime as its baseline assumption for memory performance.
The Pinnacle architecture from Riverlane and collaborators took the gross code further, estimating that 100,000 physical qubits could suffice for RSA-2048 using qLDPC codes directly.
IBM’s own Tour de Gross paper (Yoder et al., June 2025) laid out the bicycle architecture and showed that it could implement an order of magnitude more logical circuits per physical qubit than surface code architectures.
The Wills et al. paper fills a specific gap in that IBM roadmap. The standalone gross code couldn’t reach the teraquop regime at 10-3 noise. The two-gross code could, but requires a bigger chip with higher engineering complexity. Concatenation threads the needle: same small 144-qubit gross code chips connected in a rectangular grid, but algebraic structure rather than larger hardware delivers the error suppression.
For the broader competitive picture, this paper reinforces a trend I’ve been tracking in the CRQC Quantum Capability Framework: the race to fault tolerance is no longer a contest between code families in isolation. It is increasingly about hierarchical, concatenated architectures where inner codes handle local errors and outer codes provide algebraic protection against correlated failures across modules. Google’s yoked surface codes, IBM’s concatenated gross codes, and Quantinuum’s Skinny Logic codes (2:1 physical-to-logical ratio on Helios) all represent different instantiations of this principle. The specific inner codes, outer codes, and compilation strategies diverge, but the architectural pattern is converging.
Does this paper change the timeline to a cryptographically relevant quantum computer? Not materially. The teraquop regime is a necessary condition for running algorithms like Shor’s on cryptographically relevant key sizes, but reaching it in a memory simulation at 10-3 noise is several engineering generations away from reaching it on real hardware doing real computation.
What it does change is the credibility of IBM’s specific path. The bicycle architecture had a hole: the gross code’s standalone logical error rate wasn’t low enough for the algorithms that matter. This paper closes that hole with a construction that requires no new hardware capabilities, just the same 144-qubit chips connected in a grid plus classical post-processing for the outer code. If IBM can fabricate and connect these chips at scale (a big “if” that depends on yield, wiring density, and inter-module coupling fidelity), the concatenated gross code gives them a route to the error rates they need.
For CISOs and security leaders, the actionable takeaway hasn’t changed: the engineering path to fault-tolerant quantum computing continues to narrow, multiple competing architectures are making progress, and the deadlines that matter are set by regulators and clients, not by any single paper. Google Willow’s below-threshold demonstration in December 2024, Quantinuum’s 48 logical qubits on Helios in November 2025, Gidney’s sub-million-qubit RSA estimate in May 2025, IBM’s concatenated gross code now reaching the teraquop regime: each of these individually is a research result, but the accumulation of them, four in 18 months across three competing groups, tells you something about the pace.
That pace is why PQC migration cannot wait for Q-Day predictions to stabilize. The predictions keep getting closer because the engineering keeps getting better.
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