This article is part of the How to Build a Quantum Computer Deep Dive series, which covers the practical engineering of assembling quantum computers from modular components across every major qubit modality. The capstone article introduces the series and the Quantum Open Architecture model that makes it possible.
This article draws extensively on Applied Quantum‘s Systems Integration Playbook (v2.0, May 2026), the primary source for signal chain specifications, calibration sequences, integration timelines, and troubleshooting data throughout the series. Where other sources supplement the playbook, they are cited inline. Cost figures are list-price estimates from vendor disclosures and Applied Quantum’s field experience; negotiated prices vary 20–40%.
In September 2025, Diraq and imec published results in Nature that changed how the quantum computing industry thinks about manufacturing. They measured silicon quantum dot spin qubits fabricated on imec’s 300 mm industrial platform and found fidelities exceeding 99% for one- and two-qubit gate operations and above 99.9% for state preparation and measurement. These were not cherry-picked results from the best devices on the wafer. Diraq selected devices at random and achieved reproducible, high-performance metrics across multiple samples.
That distinction between “hero devices” and “randomly selected devices” is the entire argument for silicon-spin quantum computing in one sentence. Every other qubit modality fabricates processors in specialized facilities with hand-tuned processes and individually characterized chips. Silicon spin qubits are manufactured on the same 300 mm CMOS production lines that produce billions of classical transistors annually. If the fidelity holds across randomly selected devices on an industrial wafer, the path to mass production follows the same yield and cost curves that made classical computing affordable.
The silicon-spin supply chain is the youngest of the five modalities covered in this series. No vendor ships a complete, commercially available silicon-spin quantum computer today (Diraq’s roadmap targets an initial quantum computer by 2029). But the components are emerging, the fabrication thesis is validated, and two characteristics make silicon spin uniquely interesting for long-term integration planning: the qubits operate at approximately 1 K rather than the 10-20 mK required by superconducting transmons, and they can be controlled by cryo-CMOS electronics co-located on the same chip or on adjacent chiplets at the same temperature stage. Both of these properties address constraints that dominate the superconducting build.
For the physics of how silicon-spin qubits work, see my Quantum Computing Modalities series.
The cost argument for silicon-spin qubits is straightforward, and it is worth stating in terms a CTO can put in a business case.
A superconducting transmon QPU is fabricated in a specialized quantum cleanroom using niobium or tantalum sputtering on silicon or sapphire substrates, with aluminum Josephson junctions defined by shadow evaporation or Dolan bridge techniques. Each chip is individually characterized at cryogenic temperatures before shipment. QuantWare’s Gen-D chips cost approximately €60K for a 5-qubit Soprano and €300K for a 21-qubit Contralto. The fabrication process is closer to artisanal metalwork than to semiconductor manufacturing.
A silicon-spin QPU is fabricated using standard CMOS-compatible processes on 300 mm wafers: gate oxide growth, polysilicon or metal gate deposition, lithographic patterning at foundry-standard design rules, and standard back-end-of-line metallization. The substrate is isotopically enriched silicon-28 (from SOITEC, the primary supplier of enriched ²⁸Si wafers). The fabrication capacity exists at imec, GlobalFoundries, and Intel. A single 300 mm wafer can contain thousands of qubit devices. At scale, the cost per qubit follows semiconductor learning curves: as yield improves and volumes increase, cost per qubit declines exponentially with cumulative production, the same dynamic that reduced the cost of a transistor from dollars in the 1960s to fractions of a cent today.
That scaling economics argument has not yet been proven at quantum-relevant qubit counts. Diraq has demonstrated two-qubit devices. SemiQon ships 4-qubit arrays. Intel’s Tunnel Falls is a 12-qubit test chip. The jump from 12 qubits to 1,000 qubits on a single CMOS die, with uniform fidelity across the array, is an engineering challenge that the industry has not yet completed. But imec’s EUV lithography demonstration at IEDM 2025 for patterning the overlapping gate layers of quantum dot structures shows that the semiconductor industry’s most advanced patterning tools are being applied to this problem. The trajectory is toward high-volume manufacturing, even if the timeline to get there is longer than for superconducting or neutral atom.
Diraq (Sydney, Australia, UNSW spin-out led by Andrew Dzurak) is the highest-profile silicon-spin company and the one with the most advanced industrial fabrication partnership. The September 2025 Nature paper with imec is the landmark validation. Diraq advanced to DARPA QBI Stage B in November 2025 (one of 11 companies from an initial 17). Secured AUD $20M (USD $14M) from Australia’s National Reconstruction Fund Corporation in February 2026 for commercialization. Partnerships with imec, GlobalFoundries, NVIDIA, and Dell. Over 70 staff and PhD students. Technical roadmap: initial quantum computer by 2029, utility-scale performance by 2033. Architecture: silicon MOS quantum dots on isotopically enriched ²⁸Si, electron spin qubits, exchange-coupled two-qubit gates, operating at approximately 1 K. Partnership with Emergence Quantum on millikelvin-CMOS co-integration.
Intel maintains the largest silicon-spin research program of any major technology company. Tunnel Falls is a 12-qubit silicon spin test chip distributed to academic partners for benchmarking and research collaboration. Intel’s cryo-CMOS program includes Horse Ridge II (22 nm FinFET SoC operating at 3 K, 4 RF channels with FDM support for up to 128 qubits, 99.7% gate fidelity versus room-temperature baseline) and the newer Pando Tree millikelvin-stage controller. Intel’s advantage is vertical integration of CMOS fabrication expertise, but the company has not announced a timeline for a commercially available silicon-spin quantum computer. Tunnel Falls is a research platform, not a product.
SemiQon (Finland, VTT spin-out) ships 4-qubit silicon spin arrays since March 2024, the only commercially available silicon-spin QPU component today. Uses FDSOI (fully depleted silicon-on-insulator) ²⁸Si MOS quantum dots. Operates at approximately 1 K. Demonstrated cryo-CMOS transistors with record 0.3 mV/dec sub-threshold swing at 420 mK, advancing cryo-CMOS technology for scalable quantum integrated circuits in March 2026. A 12-qubit 1D array is in development. SemiQon is the closest thing the silicon-spin modality has to a QuantWare-style QOA component supplier: they sell chips, not complete systems.
Quantum Motion (UK, FDSOI silicon MOS quantum dots) is deployed at the UK National Quantum Computing Centre. Advanced to DARPA QBI Stage B (November 2025). The SiQEC project targets a rudimentary fault-tolerant unit cell by approximately 2026 using a 2×3 qubit array. Rack-form-factor integration with cryo-CMOS control.
HRL Laboratories (US, DARPA-funded) developed the spinQICK open-source control platform for exchange-only qubits. Research-grade, not commercial.
Equal1 Labs (Ireland) is building a fully integrated silicon quantum processor SoC where qubits and classical control circuits share the same die. This is the most aggressive co-integration approach.
Silicon Quantum Computing (SQC, Australia, UNSW, led by Michelle Simmons) uses donor-based qubits (phosphorus atoms in ²⁸Si) positioned with atomic precision via scanning tunneling microscope (STM) lithography. A different fabrication approach from the gate-defined quantum dots used by Diraq, Intel, and SemiQon, with unique advantages in qubit placement precision but challenges in scaling the STM lithography process.
Three properties distinguish silicon-spin integration from the superconducting and trapped-ion builds described elsewhere in this series.
Superconducting transmon qubits require cooling to 10-20 mK because the Josephson junction’s energy splitting must be much larger than the thermal energy (k_B T). Silicon-spin qubits encode information in electron spin states that are split by an external magnetic field (Zeeman splitting). The relevant energy scale is set by the applied magnetic field (typically 0.5-1.5 T), which provides a splitting large enough to operate at approximately 1 K, roughly 100 times warmer than transmon operating temperatures.
This temperature difference has three practical consequences.
First, Bluefors’ XLDHe High Power system provides 200-700 mW of cooling power at 1-1.2 K using helium-4 only. No helium-3 required. A silicon-spin build eliminates the most strategically constrained input in the quantum computing supply chain: the $2,500-per-liter isotope derived from nuclear weapons stockpile decay. For a standard dilution refrigerator, the helium-4-only XLDHe avoids the $100,000 helium-3 charge, the closed-loop gas handling system, and the entire recovery-and-purification infrastructure. The operational cost reduction is significant, and the supply chain risk reduction is even more so.
Second, the higher operating temperature is compatible with cryo-CMOS control electronics operating at the same temperature stage. This is the key enabler for solving the I/O wiring wall that constrains superconducting scaling. Instead of running hundreds of coaxial cables or Cri/oFlex ribbons from room-temperature electronics down to the millikelvin QPU, a silicon-spin system can co-locate CMOS multiplexing and control circuits at the 1 K stage, adjacent to the qubits, cutting the number of lines that must traverse the thermal gradient by orders of magnitude. Intel’s Horse Ridge II demonstrated this with 128 qubits addressable through 4 RF channels using frequency-division multiplexing.
Third, the higher temperature provides substantially more cooling power per watt of input power. At 100 mK, a dilution refrigerator provides microwatts of cooling. At 1 K, the XLDHe provides hundreds of milliwatts. This larger thermal budget accommodates the heat dissipated by co-located cryo-CMOS electronics, which is the fundamental enabling condition for the co-integration architecture.
Superconducting qubits are read out through dispersive microwave measurement at 4-8 GHz, requiring TWPAs, HEMT amplifiers, circulators, and the full readout signal chain described in the superconducting build guide. Silicon-spin qubits are read out via RF reflectometry: a single-tone RF signal (typically 100-500 MHz) is reflected off a charge sensor (a quantum point contact or single-electron transistor adjacent to the qubit quantum dot), and the spin-dependent change in the sensor’s impedance modulates the reflected signal’s phase or amplitude.
The RF reflectometry infrastructure is simpler than the transmon readout chain. Lower frequencies mean cheaper, more compact components. No TWPA or HEMT needed (though cryogenic amplifiers can improve signal-to-noise). The readout hardware for a silicon-spin system more closely resembles conventional RF test equipment than the specialized microwave signal chain of a superconducting build.
Silicon-spin qubits require a static magnetic field of 0.5-1.5 T at the QPU to define the qubit splitting. This is provided by a superconducting magnet (niobium-titanium solenoid) thermally anchored to the 4 K stage of the cryostat. The magnet field must be stable to better than 1 ppm over the computation timescale (milliseconds to seconds) and spatially uniform across the qubit array. Vector magnets (providing field control in all three spatial directions) are used for precise qubit frequency tuning. The magnet adds weight, volume, and stray-field management complexity to the cryostat design, but it is a well-understood component available from multiple suppliers (Oxford Instruments, American Magnetics, Cryomagnetics).
Silicon-spin quantum computers are not yet available as turn-key systems. The integration picture in 2026 is research-grade: academic groups and national laboratories assembling systems from SemiQon QPU chips, standard dilution refrigerators or XLDHe systems, and laboratory-built control electronics. This will change as Diraq, Intel, and Quantum Motion advance their commercialization roadmaps.
For a research-grade silicon-spin build today:
Months 1-3: Procurement. SemiQon 4-qubit QPU array (the only commercially shipping silicon-spin component). Cryostat: Bluefors XLDHe High Power (He-4 only, 1 K operation) or standard dilution refrigerator (LD/XLD class, if millikelvin operation is desired for flexibility). Superconducting vector magnet. RF reflectometry hardware: signal generators, directional couplers, cryogenic amplifiers (optional), room-temperature digitizers. DC voltage sources for gate electrodes (dozens of channels for a 4-qubit device, scaling to hundreds for larger arrays). FPGA-based control: Qblox QCM baseband modules, or HRL’s open-source spinQICK platform, or custom DAC boards.
Months 3-5: Facility and cryostat commissioning. Facility preparation comparable to superconducting (vibration isolation, EMI shielding, power conditioning), minus the helium-3 storage and recovery infrastructure if using XLDHe. Cryostat installation and cool-down verification. Magnet commissioning: ramp to operating field, verify field homogeneity, characterize residual vibration from magnet forces.
Months 5-7: QPU installation and characterization. Mount SemiQon chip on sample carrier. Wire-bond or flip-chip to the carrier’s gate electrodes and RF reflectometry lines. Install in cryostat. Cool down. Characterize quantum dots: tune gate voltages to define single-electron occupation in each dot, map the charge stability diagram, identify the spin readout signal via Pauli spin blockade. This is more labor-intensive than superconducting QPU bring-up because each quantum dot requires individual voltage tuning across multiple gate electrodes, and the parameter space is larger than for transmon frequency tuning.
Months 7-9: Qubit characterization and gate calibration. Single-qubit gates via electric-dipole spin resonance (EDSR) or electron spin resonance (ESR): calibrate drive frequency, amplitude, and pulse shape. T1 and T2 measurements. Single-qubit randomized benchmarking. Two-qubit gates via exchange interaction: tune the barrier gate between adjacent dots to control the exchange coupling strength. Two-qubit gate calibration and benchmarking. For a 4-qubit SemiQon array, expect 2-4 weeks with experienced personnel.
Total timeline: 6-9 months from procurement to characterized qubits, comparable to a superconducting build but with more manual tuning at the QPU characterization stage. Automated tuning algorithms (machine-learning-based gate voltage optimization) are an active research area that will compress this timeline as the field matures.
Charge noise. Electric field fluctuations from interface traps and defects at the Si/SiO₂ boundary shift quantum dot energy levels and decohere the qubit. Charge noise is the dominant error source for silicon-spin qubits. Imec’s optimized 300 mm platform achieved charge noise levels of 0.6 µeV/√Hz at 1 Hz, the lowest values on a fab-compatible platform at the time of publication. Further improvement requires even higher isotopic enrichment of the silicon channel layer (reducing residual ²⁹Si nuclear spins) and continued interface engineering.
Valley splitting variability. Silicon’s conduction band has multiple energy minima (valleys). The energy splitting between valley states must be large enough that the qubit operates in a single valley. Valley splitting is sensitive to interface roughness and varies across devices on the same wafer. This is one of the main sources of device-to-device variability in silicon-spin QPUs, and a key challenge for the “randomly selected devices” thesis. Imec and Diraq’s Nature paper demonstrated reproducible performance, but larger arrays will test whether valley splitting uniformity holds at scale.
Gate voltage crosstalk. Each quantum dot is defined by multiple gate electrodes (plunger, barrier, and reservoir gates), and the voltage on one gate affects neighboring dots through capacitive coupling. As arrays grow, managing this crosstalk becomes a combinatorial tuning problem. Virtual gates (linear combinations of physical gate voltages that independently control individual dot parameters) are the standard mitigation, but defining the virtual-gate matrix requires characterization of the full crosstalk matrix for every device.
Magnetic field stability. Fluctuations in the applied magnetic field directly modulate qubit frequencies. The superconducting magnet must be persistent-mode or actively stabilized. External magnetic field noise from building infrastructure, nearby equipment, and even passing vehicles couples through imperfect shielding. The same mu-metal and superconducting shielding used for transmon QPUs applies here, with the additional consideration that the deliberately applied 0.5-1.5 T field creates stray fields that must be managed to avoid affecting other equipment in the lab.
Silicon-spin systems require a skill set that overlaps with both superconducting (cryogenics, RF engineering) and semiconductor fabrication (device physics, gate voltage tuning):
One cryogenic engineer for the dilution refrigerator or XLDHe system, magnet operation, and sample environment management. One to two quantum device physicists for gate voltage tuning, quantum dot characterization, and qubit calibration. This is the most specialized role: it requires deep understanding of semiconductor device physics, charge stability diagrams, and spin manipulation. Candidates typically come from condensed matter physics PhD programs focused on semiconductor quantum dots. One RF/microwave engineer for the reflectometry readout chain and control electronics. One software/automation engineer for control system integration, machine-learning-based auto-tuning, and data analysis.
For a single research system: 4-6 FTEs. The quantum device physicist role is the hardest to fill, comparable to the laser specialist challenge in trapped-ion systems.
As the modality matures and automated tuning replaces manual gate voltage optimization, the skill requirements will shift from device physics toward systems engineering, following the same pattern that superconducting followed as manual calibration gave way to Q-CTRL and QuantrolOx automation.
Silicon spin is not ready for production procurement in 2026. No vendor sells a complete silicon-spin quantum computer. SemiQon’s 4-qubit arrays are the only commercially shipping QPU component. The modality is 3-5 years behind superconducting and neutral atom in terms of system-level readiness.
But the long-term argument is strong enough that organizations planning quantum compute infrastructure for the late 2020s and beyond should track silicon spin closely. The CMOS fabrication thesis, if it delivers on the yield and cost curves that the Diraq/imec results suggest, would produce qubits at costs orders of magnitude below current transmon pricing. The helium-3-free cryogenic pathway eliminates the most constrained supply chain dependency. The cryo-CMOS co-integration path is the only credible engineering solution to the I/O wiring wall at the million-qubit scale.
The benchmarks that would accelerate silicon-spin procurement timelines: a verified multi-qubit array (10+ qubits) with uniform fidelity above 99% across all devices on a single die, demonstrated on an industrial 300 mm wafer. Diraq’s DARPA QBI Stage B work is the program most likely to produce this result within the next 12-18 months. If it does, the timeline for the first commercial silicon-spin quantum computer moves from 2029 to potentially 2027-2028.
For the cryogenic infrastructure that silicon spin shares with superconducting (minus helium-3), the HPC integration path, and the cost comparison across modalities, see the corresponding articles in this series.
My company - Applied Quantum - helps governments, enterprises, and investors prepare for both the upside and the risk of quantum technologies. We deliver concise board and investor briefings; demystify quantum computing, sensing, and communications; craft national and corporate strategies to capture advantage; and turn plans into delivery. We help you mitigate the quantum risk by executing crypto‑inventory, crypto‑agility implementation, PQC migration, and broader defenses against the quantum threat. We run vendor due diligence, proof‑of‑value pilots, standards and policy alignment, workforce training, and procurement support, then oversee implementation across your organization. Contact me if you want help.
此内容由惯性聚合(RSS阅读器)自动聚合整理，仅供阅读参考。 原文来自 — 版权归原作者所有。