June 1, 2026 — D-Wave Quantum Inc. (NYSE: QBTS) unveiled a gate-model quantum computing roadmap at its first Investor Day on June 1, targeting a 100-logical-qubit, fault-tolerant superconducting system capable of executing over one million operations by 2032. The announcement was made at the New York Stock Exchange, where CEO Alan Baratz described the company’s superconducting dual-rail architecture as “a fundamentally different approach to fault-tolerant quantum computing.”
The bottom line: the company that built its identity on quantum annealing is now making a public, milestone-driven commitment to the gate-model systems it spent two decades avoiding. Whether it can execute against competitors with years of head start is the open question.
Staged milestones chart a progression of physical-qubit systems before transitioning to logical qubits:
The roadmap is built on dual-rail qubit technology acquired through D-Wave’s $550 million purchase of Quantum Circuits Inc. (QCI), completed in January 2026. QCI was founded by Rob Schoelkopf, the Yale physicist who co-invented the transmon qubit and developed the dual-rail encoding approach. Schoelkopf now leads D-Wave’s gate-model R&D from a center in New Haven, Connecticut.
D-Wave claims its dual-rail architecture detects approximately 90% of errors at the hardware level during computation, converting common noise into identifiable “erasure” errors at the single-qubit level. The company reports 99.9% two-qubit gate fidelities with error detection enabled. D-Wave argues this built-in error detection approach could reduce the number of physical qubits required per logical qubit by up to an order of magnitude compared to conventional transmon architectures.
The company positions Lambda as its key metric for measuring progress toward fault tolerance. Lambda quantifies how rapidly errors decrease as more error correction capability is added; the broader industry has demonstrated Lambda values around 2, meaning each increment in error correction halves the error rate. D-Wave’s roadmap targets Lambda = 10, which would reduce errors by a factor of 10 for each increment.
D-Wave also claimed during the presentation that superconducting systems can run quantum error correction cycles 100 to 1,000 times faster than neutral-atom or trapped-ion systems, a speed advantage that the company argues compensates for its later start in the gate-model race.
The gate-model roadmap was announced during a period of active capital-raising for D-Wave. On May 21, the company signed a Letter of Intent for $100 million in proposed funding under the U.S. CHIPS and Science Act, administered by the Department of Commerce. If finalized, D-Wave would issue $100 million in common stock to the U.S. government. The funding would support development at D-Wave’s planned facility in Boca Raton, Florida, along with existing R&D centers in New Haven and Burnaby, British Columbia.
D-Wave’s Q1 2026 earnings, reported on May 12, showed revenue of $2.9 million against analyst expectations of $4.14 million. Bookings, however, reached $33.4 million, and the company pointed to a $20 million agreement for Florida Atlantic University to purchase and install an Advantage2 annealing system.
QBTS shares slipped 1.4% in premarket trading on the day of the announcement. Stifel reiterated its Buy rating and $35 price target following the Investor Day, noting that D-Wave quantified annealing economics for the first time and presented long-term segment mix and margin profiles. The company holds approximately $553 million in net cash.
D-Wave entering gate-model quantum computing carries a particular historical weight. This is the company that spent over two decades telling the industry that the gate-model approach was the wrong path, that quantum annealing was the faster route to practical quantum computing, and that qubit count mattered more than gate fidelity. Now it has paid $550 million for the right to compete in the very arena it once dismissed.
The irony runs deeper than corporate strategy. Rob Schoelkopf, now leading D-Wave’s gate-model program, co-invented the transmon qubit at Yale. The transmon is the workhorse of IBM, Google, and every other superconducting gate-model effort. D-Wave’s original identity was built on rejecting the transmon approach in favor of flux qubits and annealing. Having the inventor of the transmon now build D-Wave’s gate-model future is a remarkable inversion.
I don’t say any of this to be flippant. Companies pivot, and a pivot backed by a credible technical thesis can succeed. The question is whether D-Wave’s thesis survives contact with the competitive reality.
The 90% error-detection claim for dual-rail qubits is the core of D-Wave’s differentiation argument. Dual-rail encoding uses two coupled superconducting cavities to represent a qubit, and when a photon is lost from one cavity, the error can be flagged by measuring whether the photon is still present. This converts a difficult-to-correct “loss” error into a detected “erasure” error, which is easier to handle in error correction codes.
Peer-reviewed publications from the Yale group support the physics here, and the erasure-detection concept has theoretical backing. I covered dual-rail qubits in my superconducting modality article, and the approach has real promise for reducing the physical-qubit overhead of error correction.
The caveat: D-Wave’s 99.9% two-qubit fidelity figure is reported with error detection, meaning post-selected. Post-selection discards runs where errors were detected, keeping only the “clean” results. That’s useful for benchmarking the underlying qubit quality, but it inflates the apparent fidelity because you’re throwing away the bad outcomes. The operationally relevant question is: what’s the net computation rate after you account for all the discarded runs? A 99.9% fidelity with a 10% discard rate produces different computational throughput than 99.9% fidelity with a 1% discard rate. D-Wave has not published the discard rate.
For context, Quantinuum’s Helios system demonstrated 99.921% all-pairs two-qubit gate fidelity without erasure-based post-selection, using 98 physical trapped-ion qubits. Google’s Willow achieved below-threshold error suppression on a 105-qubit superconducting chip using conventional transmon qubits and surface codes. Both of these results are demonstrated on operational hardware, not roadmap targets. D-Wave’s 17-physical-qubit system, the first milestone, is slated for later this year.
The 2032 target of 100 logical qubits at over one million operations puts D-Wave behind several competitors who have published more aggressive timelines:
D-Wave’s 2032 timeline would place it at roughly where IBM plans to be three years earlier, and where Quantinuum plans to be two years earlier. These are all roadmap targets, and roadmaps in this industry have a mixed track record. But the competitive gap is real: D-Wave is starting from 0 demonstrated gate-model qubits, while IBM has Heron (156 qubits) shipping, Quantinuum has Helios operational, and Google has published Willow results.
D-Wave’s counterargument centers on the physical-qubit efficiency of dual-rail encoding. If dual-rail qubits actually require an order of magnitude fewer physical qubits per logical qubit than conventional transmons, then D-Wave’s smaller systems could achieve logical qubit counts that require much larger processors from competitors. That would change the economics of the race considerably. But the “order of magnitude fewer” claim is a projection, not a demonstration. The first data point will be the 17-qubit system later this year, which D-Wave says will show logical error rates 2× below physical rates. That would be a meaningful result if achieved.
The Lambda target deserves particular attention. A Lambda of 10 would mean that each step up in code distance reduces the error rate by 10×, compared to the roughly 2× that Google demonstrated with Willow. If achievable, this would be significant for the resource estimates that matter for fault-tolerant computing. The number of physical qubits needed for a given number of logical qubits scales steeply with Lambda; a Lambda of 10 versus 2 would produce vastly different physical-qubit requirements.
However, no group anywhere has demonstrated Lambda = 10 in hardware. Google’s Willow achieved Lambda ≈ 2.14 across code distances 3, 5, and 7 on a conventional surface code with transmons. Lambda values tend to be constrained by the ratio of physical error rate to the threshold error rate, which is a property of the code and hardware combination. Achieving Lambda = 10 would require physical error rates well below the code threshold, which in turn requires gate fidelities and measurement fidelities at levels that have not been demonstrated in any superconducting system.
D-Wave’s argument is that dual-rail erasure detection changes the error-correction calculus enough to reach these numbers with fewer physical qubits and at higher effective Lambda. The theory supports some version of this claim: erasure errors are cheaper to correct than Pauli errors, and codes optimized for erasure noise can achieve higher thresholds. Whether this translates to Lambda = 10 in practice is an experimental question that will take years to answer. I’ll track this against my CRQC Quantum Capability Framework, specifically the below-threshold operation and quantum error correction capabilities, as D-Wave publishes data.
The roadmap announcement comes at a fraught moment for D-Wave’s credibility narrative. In March 2025, the company published a Science paper claiming quantum supremacy for its Advantage2 annealer on a materials simulation problem. D-Wave said its annealer solved the problem in minutes while the Frontier supercomputer would require nearly one million years.
On May 21, 2026, just 11 days before the Investor Day, physicists at the Simons Foundation’s Flatiron Institute and Boston University published a paper in Science showing that a classical tensor-network algorithm could simulate parts of the same problem with comparable accuracy. Joseph Tindall, a researcher at the Flatiron Institute, reportedly ran many of the initial calculations on a laptop. The paper does not fully refute D-Wave’s claim (the classical algorithm solved “parts of” the problem, and the full comparison is nuanced), but it raises serious questions about whether D-Wave’s supremacy result was specific to a narrow problem instance rather than a general computational advantage.
The timing matters because D-Wave’s Investor Day narrative rested on credibility: the company positioned itself as the only dual-platform quantum computing company, with a proven track record in annealing and a credible new path to gate-model fault tolerance. Having the annealing supremacy claim challenged days earlier weakens the “proven track record” half of that argument.
From a CRQC and Q-Day perspective, D-Wave’s gate-model roadmap has no meaningful impact on the timeline. A 100-logical-qubit system by 2032 is orders of magnitude below the thousands of logical qubits needed to run Shor’s algorithm against RSA-2048 or ECC. Even the most optimized recent resource estimates, such as Gidney’s 2025 work, require roughly 4 million physical qubits (or several thousand logical qubits at high code distances). D-Wave’s 2032 target is a rounding error on that scale.
The dual-rail approach could contribute indirectly, however. If erasure-based error correction proves as efficient as its proponents claim, the technique could influence resource estimates across the industry, including in systems built by IBM, Google, or others. The concept is not exclusive to D-Wave; other groups (including the Yale lab where it originated) are exploring dual-rail and erasure-based approaches independently. The question is whether D-Wave can productize this faster than academic groups can publish it.
Three metrics will determine whether this roadmap is serious or vaporware:
The 17-qubit system later this year is the first real test. D-Wave claims it will demonstrate logical error rates 2× below physical rates. If that holds up under independent benchmarking, it validates the dual-rail erasure thesis at small scale.
The 49-qubit system in 2027 targets a 20× error reduction, which would start to approach Google Willow’s Lambda ≈ 2.14 result, but with a structurally different architecture. Missing this milestone would signal that the dual-rail advantage is smaller than projected.
The Lambda value itself. D-Wave can talk about Lambda = 10 all it wants, but the actual measured Lambda on their first few systems will tell us whether the theoretical advantage of erasure detection translates into practice. Lambda values are measurable, falsifiable quantities, and I expect D-Wave to publish (or be pressed to publish) these numbers as the systems come online.
For readers tracking the broader competitive picture, D-Wave’s entry adds another data point to an increasingly crowded superconducting roadmap. But until the 17-qubit system produces peer-reviewed results, this is a press release, not a capability. Roadmaps in quantum computing have a well-documented history of slipping, being revised, or quietly retired. D-Wave’s own history includes multiple roadmap resets over its 27 years.
The company’s financial position adds urgency. With $2.9 million in quarterly revenue, ongoing cash burn, and a business model that still depends heavily on stock issuance (the QCI acquisition, the CHIPS Act LOI), D-Wave needs its gate-model story to attract capital. The 2032 timeline is long enough that investors are being asked to fund six years of R&D before seeing the target system. That’s a substantial ask for a company whose annealing supremacy claim just took a hit.
I’ll update my D-Wave company profile and the superconducting qubits modality article to reflect this roadmap. The dual-rail approach warrants a dedicated section in the modality coverage.
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