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Cankun Zhao, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University., State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, 100084, China.
Bohan Yang, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University., State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, 100084, China.
Wenping Zhu, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University., State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, 100084, China.
Hanning Wang, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University., State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, 100084, China.
Min Zhu, Wuxi Micro Innovation Integrated Circuit Design Co., Ltd, Jiangsu Wuxi, China.
Leibo Liu, Beijing National Research Center for Information Science and Technology, School of Integrated Circuits, Tsinghua University., State Key Laboratory of Cryptography and Digital Economy Security, Tsinghua University, Beijing, 100084, China.
Emerging 6G communication systems impose unprecedented requirements on cryptographic primitives, demanding ultra-high throughput, low latency, and strong resistance to implementation-level attacks. LOL2.0 is a recently proposed stream cipher framework that achieves high software efficiency and strong security in post-quantum settings. While several stream ciphers have been proposed to address performance demands, side-channel-protected hardware implementations capable of sustaining 6G-class throughput remain largely unexplored. In this work, we present the first side-channel-protected hardware implementation that meets the 6G-class throughput demand. Focusing on the LOL2.0 stream cipher framework, we leverage Time Sharing Masking to achieve first-order security under the glitch-extended probing model. This design realizes full-phase protection covering initialization, keystream generation, and tag generation. To address diverse deployment requirements, we design two masked architectures: a compact variant optimized for area and randomness efficiency, and a fast variant targeting the maximum achievable throughput. The proposed fast implementations achieve peak throughputs of 183 Gbps and 142 Gbps for the unmasked and masked configurations, respectively. Meanwhile, the compact architecture reduces hardware cost by achieving areas as low as 23.25 kGE and 141.98 kGE in unmasked and masked designs, respectively, while still maintaining competitive throughput. Security is validated through practical side-channel evaluations using Test Vector Leakage Assessment on FPGA platforms. Across up to 100 million measured power traces, no statistically significant first-order leakage is observed for any protected configuration. Overall, this work realizes side-channel-protected stream cipher hardware that sustains ultra-high throughput, providing a concrete path toward secure cryptographic deployment in future 6G communication systems.
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