Paper 2026/1052

Full Key Recovery of Masked PRESENT on an Out-of-Order RISC-V Processor: A First Reported Case Study

Nimish Mishra, Indian Institute of Technology Kharagpur

Sarani Bhattacharya, Indian Institute of Technology Kharagpur

Debdeep Mukhopadhyay, Indian Institute of Technology Kharagpur

Abstract

Masking-based countermeasures such as Threshold Implementations and Probe-Isolating Non-Interference (PINI) are commonly assumed to protect cryptographic software against side-channel leakage by maintaining isolation between secret shares. In this work, we show that this assumption can break on modern out-of-order (OoO) processors due to backend microarchitectural effects that are not visible at the ISA level. We develop a trace-driven analysis framework that reconstructs physical-register reuse and backend execution interactions from OoO RISC-V pipeline traces. The framework identifies leakage arising from backend physical-register reuse and transient overlap of masked-share operations inside OoO execution structures. We evaluate the framework on a masked PRESENT implementation and composable PINI gadgets. Our analysis shows that although rotated-share computations protect selected nonlinear operations, affine share pairs remain directly represented in the architectural execution state. OoO register renaming can therefore induce physical-register transitions of the form \[ \operatorname{HW}_{\mathrm{bit}}(a_0[b]\oplus a_1[b]), \] which reconstruct affine PRESENT intermediates and create key-dependent leakage. We validate the leakage experimentally in two stages. First, using a modified gem5 OoO RISC-V model, we attribute the dominant leakage source to backend physical-register reuse and demonstrate first-round PRESENT subkey recovery from masked execution traces. Second, on a real SiFive P550-class OoO RISC-V processor, we perform a temperature-based side-channel experiment using Linux-accessible thermal telemetry and recover 60 out of 80 key bits from the masked PRESENT implementation. The results establish a complete cross-layer leakage path from masked software execution to OoO backend interactions, physical-register transitions, thermal behavior, and practical key recovery on real hardware. Our findings demonstrate that masking schemes appearing secure under software-level analysis may still leak on OoO processors, motivating hardware-aware verification of masked software deployments.

@misc{cryptoeprint:2026/1052,
      author = {Siddhartha Chowdhury and Nimish Mishra and Sarani Bhattacharya and Debdeep Mukhopadhyay},
      title = {Full Key Recovery of Masked {PRESENT} on an Out-of-Order {RISC}-V Processor: A First Reported Case Study},
      howpublished = {Cryptology {ePrint} Archive, Paper 2026/1052},
      year = {2026},
      url = {https://eprint.iacr.org/2026/1052}
}