Paper 2025/1490

Accelerating FALCON: Speed Records for FALCON's SamplerZ on Xilinx FPGAs

Rahul Magesh, North Carolina State University

Elif Bilge Kavun, Barkhausen Institut

Aydin Aysu, North Carolina State University

Abstract

FALCON is a NIST-selected post-quantum digital signature scheme whose performance bottleneck lies in the SamplerZ subroutine for discrete Gaussian sampling. We present a throughput-optimized, custom hardware implementation of SamplerZ that introduces several architectural and algorithmic innovations to significantly accelerate signature generation. Our design incorporates a datapath-aware floating-point arithmetic pipeline that strategically balances latency and resource utilization. Our novel algorithmic innovations include an Estrin's Scheme-based polynomial evaluator and a constant-latency BerExp routine using floating-point exponentiation IP to eliminate fixed-point decomposition critical paths. Additionally, we optimize rejection handling through parallel sampling loops and propose a speed-optimized flooring circuit. These advancements lower the sampling time by 55%-81% and overall FALCON signature generation time by 36%-53% compared to the state-of-the-art FPGA implementation. In a landmark result, our work is the first to demonstrate a Xilinx FPGA SamplerZ design that outperforms state-of-the-art software (by 15%) and ASIC (by 16%) designs, advancing the practical deployment of post-quantum signatures on reconfigurable hardware.

@misc{cryptoeprint:2025/1490,
      author = {Sharath Pendyala and Rahul Magesh and Elif Bilge Kavun and Aydin Aysu},
      title = {Accelerating {FALCON}: Speed Records for {FALCON}'s {SamplerZ} on Xilinx {FPGAs}},
      howpublished = {Cryptology {ePrint} Archive, Paper 2025/1490},
      year = {2025},
      url = {https://eprint.iacr.org/2025/1490}
}