IBM has introduced a sub-1 nanometer chip technology built around a new transistor architecture called nanostack.
The company said the technology uses a 0.7-nanometer, or 7-angstrom, node. IBM described it as the world’s first sub-1 nanometer chip technology.
The 0.7-nanometer label refers to a process generation rather than the exact physical size of every transistor feature. According to IBM, modern node names refer to manufacturing technology generations, not a single measured dimension on a chip.
The design can place nearly 100 billion transistors on a chip area roughly the size of a fingernail, according to the company. That is about twice the transistor density of the 2-nanometer chip technology IBM announced in 2021.
The new technology is projected to deliver up to 50% more performance or 70% better energy efficiency than IBM’s 2-nanometer node chips, according to the company. IBM did not announce a commercial processor based on the technology.
The announcement refers to a chip technology and transistor architecture rather than a processor entering production. The company said the earliest adoption of nanostack at the sub-1 nanometer node could come within five years.
The technology is based on IBM’s nanostack transistor structure. Instead of relying only on lateral scaling across a flat chip surface, the design vertically stacks and staggers transistors using three-dimensional sequential integration.
Nanostack is a three-dimensional, nanosheet-based design that builds on nanosheet technology, according to IBM. Nanosheet transistors use thin horizontal sheets surrounded by a gate. The new architecture extends that approach by placing transistor layers above one another, allowing more devices to fit into the same chip area.
IBM Research describes NanoStack as a sequential stacking CMOS transistor architecture for the 7-angstrom node and beyond. The design uses stacked nanosheet channels and thin dielectric bonding to place transistor layers above one another.
The stacked structure also allows different material combinations to be used within each layer. Each stacked layer can be tuned for different performance and power requirements, according to IBM.
The architecture has been experimentally validated through ultra-thin dielectric bonding in CMOS integration, dual-channel engineering, and functional CMOS inverter operation, according to IBM. The company said the validation work included physical integration and functional CMOS inverter operation.
The company has not said the technology is ready for commercial production. Details on manufacturing yield, production cost, and a confirmed fabrication partner have not been disclosed.
The technology also addresses SRAM, a type of memory used inside processors for fast data access. Research presented at VLSI 2026 showed that nanostack can reduce SRAM cell size by 40%, according to IBM.
On-chip memory does not always shrink at the same pace as logic transistors, leaving SRAM area as a design constraint in advanced processors. Smaller SRAM cells can help chip designers place more memory closer to compute units.
The SRAM figure was presented as part of IBM’s VLSI 2026 research. While performance and energy-efficiency figures are projections for the node, the SRAM figure refers to a scaling result presented as part of that research.
The company linked the SRAM improvement to AI workloads and high-bandwidth data access. It did not name specific products that will use the technology.
Reuters reported that SRAM is heavily used in AI-focused chips from companies including Nvidia, Groq, and Cerebras Systems, which currently rely on TSMC. The company did not say whether any of those firms would use nanostack or whether the technology has been licensed for AI accelerators.
The earliest adoption of nanostack technology at the sub-1 nanometer node could come within five years, according to IBM. The company has not announced a manufacturing partner for the technology.
Reuters reported that IBM has previously licensed chip technologies to Samsung and Japan’s Rapidus, but no partner has been announced for nanostack.
The work is being conducted with partners at IBM’s semiconductor research facility in Albany, New York. The site is expected to receive a High Numerical Aperture Extreme Ultraviolet lithography tool, or High NA EUV, from ASML, according to IBM.
High NA EUV is designed to print smaller circuit features with greater precision than current EUV systems. IBM said it has worked with Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions on High NA EUV processes and tools that have already produced working devices.
IBM and Lam Research announced a five-year collaboration in March 2026 focused on new processes and materials for sub-1 nanometer logic scaling. The work includes High NA EUV process development, along with materials and fabrication techniques needed for smaller logic nodes, according to the companies.
Details on lithography, deposition, etching, bonding, or process-control steps for commercial nanostack manufacturing have not been provided.
Intel said at the 2026 VLSI Symposium that Intel 18A-P, a performance enhancement in the Intel 18A family, had entered risk production. Risk production is an early manufacturing stage before commercial manufacturing.
IBM has not announced a commercial processor, manufacturing partner, or production start date for nanostack.
The company has previously licensed chip technologies to Samsung and Rapidus. It said nanostack provides a path for further scaling, but it has not provided details on production costs, manufacturing yield, or commercial availability.
Details on yield, defect control, design rules, tooling availability, and customer adoption have not been provided.
IBM shares rose more than 6% in premarket trading after the announcement before paring gains to about 1.9%. The stock remains down about 11% for the year.
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